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Tue, 1 Sep 2026 08:52:48 +0000 From: Jamin Lin To: =?iso-8859-1?Q?Daniel_P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Eric Blake , Markus Armbruster , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: Jamin Lin , Troy Lee Subject: [PATCH v4 8/9] hw/misc/aspeed_sbc: Support the ECDSA verify command Thread-Topic: [PATCH v4 8/9] hw/misc/aspeed_sbc: Support the ECDSA verify command Thread-Index: AQHdOe9Dnx2Wl1OVLk2ZRp85jdWqMQ== Date: Tue, 1 Sep 2026 08:52:48 +0000 Message-ID: <20260901085238.995968-9-jamin_lin@aspeedtech.com> References: <20260901085238.995968-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260901085238.995968-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The AST10x0 secure boot controller register block also hosts an ECDSA=0A= engine. Emulate its secp384r1 "verify" command: on a trigger write to=0A= the command register, read the public key, signature and SHA-384 digest=0A= that the firmware staged in the SEC SRAM and defer the verification to the= =0A= crypto akcipher backend, reporting the result through the status=0A= register.=0A= =0A= The model reads its operands from the SEC SRAM through a dedicated=0A= address space, using a 'sram' link. The SEC SRAM is mapped at offset 0=0A= of that address space, so the engine addresses each operand directly=0A= with its SRAM-relative offset.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/misc/aspeed_sbc.c | 141 +++++++++++++++++++++++++++++++++++++++++++=0A= hw/misc/trace-events | 2 +=0A= 2 files changed, 143 insertions(+)=0A= =0A= diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c=0A= index f10f7ac578..5c193d9086 100644=0A= --- a/hw/misc/aspeed_sbc.c=0A= +++ b/hw/misc/aspeed_sbc.c=0A= @@ -10,11 +10,13 @@=0A= =0A= #include "qemu/osdep.h"=0A= #include "qemu/log.h"=0A= +#include "qemu/cutils.h"=0A= #include "qemu/error-report.h"=0A= #include "hw/core/qdev-properties.h"=0A= #include "hw/misc/aspeed_sbc.h"=0A= #include "qapi/error.h"=0A= #include "migration/vmstate.h"=0A= +#include "crypto/akcipher.h"=0A= #include "trace.h"=0A= =0A= #define R_PROT (0x000 / 4)=0A= @@ -24,8 +26,22 @@=0A= #define R_CAMP1 (0x020 / 4)=0A= #define R_CAMP2 (0x024 / 4)=0A= #define R_QSR (0x040 / 4)=0A= +#define R_SEC_TRIGGER (0x0bc / 4)=0A= +=0A= +/*=0A= + * SEC SRAM layout for a secp384r1 ECDSA verify operation. All operands ar= e=0A= + * 48-byte big-endian values.=0A= + */=0A= +#define ECDSA_SRAM_QX 0x2080=0A= +#define ECDSA_SRAM_QY 0x20c0=0A= +#define ECDSA_SRAM_R 0x21c0=0A= +#define ECDSA_SRAM_S 0x2200=0A= +#define ECDSA_SRAM_M 0x2240=0A= +#define ECDSA_P384_COORD_LEN 48=0A= =0A= /* R_STATUS */=0A= +#define ECDSA_VERIFY_PASS BIT(21)=0A= +#define ECDSA_VERIFY_DONE BIT(20)=0A= #define ABR_EN BIT(14) /* Mirrors SCU510[11] */=0A= #define ABR_IMAGE_SOURCE BIT(13)=0A= #define SPI_ABR_IMAGE_SOURCE BIT(12)=0A= @@ -42,6 +58,10 @@=0A= #define OTP_MEM_IDLE BIT(1)=0A= #define OTP_COMPARE_STATUS BIT(0)=0A= =0A= +/* R_SEC_TRIGGER */=0A= +#define ECDSA_CMD_TRIGGER BIT(1)=0A= +#define RSA_CMD_TRIGGER BIT(0)=0A= +=0A= /* QSR */=0A= #define QSR_RSA_MASK (0x3 << 12)=0A= #define QSR_HASH_MASK (0x3 << 10)=0A= @@ -220,10 +240,111 @@ static void aspeed_sbc_handle_command(void *opaque, = uint32_t cmd)=0A= s->regs[R_STATUS] |=3D (OTP_MEM_IDLE | OTP_IDLE);=0A= }=0A= =0A= +static void sbc_ecdsa_hexdump(const char *desc, const char *buf, size_t si= ze)=0A= +{=0A= + g_autoptr(GString) str =3D g_string_sized_new(64);=0A= + size_t len;=0A= + size_t i;=0A= +=0A= + for (i =3D 0; i < size; i +=3D len) {=0A= + len =3D MIN(16, size - i);=0A= + g_string_truncate(str, 0);=0A= + qemu_hexdump_line(str, buf + i, len, 1, 4);=0A= + trace_aspeed_sbc_ecdsa_hexdump(desc, i, str->str);=0A= + }=0A= +}=0A= +=0A= +/*=0A= + * The hardware only supports ECDSA secp384r1 (NIST P-384). The firmware h= as=0A= + * already staged the public key, signature and digest in the SEC SRAM; re= ad=0A= + * them out and defer the actual verification to the crypto backend.=0A= + */=0A= +static bool aspeed_sbc_ecdsa_verify(AspeedSBCState *s)=0A= +{=0A= + QCryptoAkCipherOptions opts =3D {=0A= + .alg =3D QCRYPTO_AK_CIPHER_ALGO_ECDSA,=0A= + .u.ecdsa.curve_id =3D QCRYPTO_CURVE_ID_SECP384R1,=0A= + };=0A= + g_autoptr(QCryptoAkCipher) akcipher =3D NULL;=0A= + uint8_t pubkey[ECDSA_P384_COORD_LEN * 2];=0A= + uint8_t sig[ECDSA_P384_COORD_LEN * 2];=0A= + uint8_t dgst[ECDSA_P384_COORD_LEN];=0A= + Error *err =3D NULL;=0A= +=0A= + if (!qcrypto_akcipher_supports(&opts)) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: ECDSA secp384r1 is not supported by the crypto = "=0A= + "backend\n", __func__);=0A= + return false;=0A= + }=0A= +=0A= + if (address_space_read(&s->sram_as, ECDSA_SRAM_QX,=0A= + MEMTXATTRS_UNSPECIFIED, pubkey,=0A= + ECDSA_P384_COORD_LEN) !=3D MEMTX_OK) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: failed to read ECDSA QX from SEC SRAM\n", __fun= c__);=0A= + return false;=0A= + }=0A= + if (address_space_read(&s->sram_as, ECDSA_SRAM_QY,=0A= + MEMTXATTRS_UNSPECIFIED,=0A= + pubkey + ECDSA_P384_COORD_LEN,=0A= + ECDSA_P384_COORD_LEN) !=3D MEMTX_OK) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: failed to read ECDSA QY from SEC SRAM\n", __fun= c__);=0A= + return false;=0A= + }=0A= + if (address_space_read(&s->sram_as, ECDSA_SRAM_R,=0A= + MEMTXATTRS_UNSPECIFIED, sig,=0A= + ECDSA_P384_COORD_LEN) !=3D MEMTX_OK) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: failed to read ECDSA R from SEC SRAM\n", __func= __);=0A= + return false;=0A= + }=0A= + if (address_space_read(&s->sram_as, ECDSA_SRAM_S,=0A= + MEMTXATTRS_UNSPECIFIED, sig + ECDSA_P384_COORD_= LEN,=0A= + ECDSA_P384_COORD_LEN) !=3D MEMTX_OK) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: failed to read ECDSA S from SEC SRAM\n", __func= __);=0A= + return false;=0A= + }=0A= + if (address_space_read(&s->sram_as, ECDSA_SRAM_M,=0A= + MEMTXATTRS_UNSPECIFIED, dgst,=0A= + ECDSA_P384_COORD_LEN) !=3D MEMTX_OK) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: failed to read ECDSA M from SEC SRAM\n",=0A= + __func__);=0A= + return false;=0A= + }=0A= +=0A= + if (trace_event_get_state_backends(TRACE_ASPEED_SBC_ECDSA_HEXDUMP)) {= =0A= + sbc_ecdsa_hexdump("pubkey", (char *)pubkey, sizeof(pubkey));=0A= + sbc_ecdsa_hexdump("signature", (char *)sig, sizeof(sig));=0A= + sbc_ecdsa_hexdump("digest", (char *)dgst, sizeof(dgst));=0A= + }=0A= +=0A= + akcipher =3D qcrypto_akcipher_new(&opts, QCRYPTO_AK_CIPHER_KEY_TYPE_PU= BLIC,=0A= + pubkey, sizeof(pubkey), &err);=0A= + if (!akcipher) {=0A= + qemu_log_mask(LOG_GUEST_ERROR, "%s: %s\n", __func__,=0A= + error_get_pretty(err));=0A= + error_free(err);=0A= + return false;=0A= + }=0A= +=0A= + if (qcrypto_akcipher_verify(akcipher, sig, sizeof(sig),=0A= + dgst, sizeof(dgst), &err) !=3D 0) {=0A= + error_free(err);=0A= + return false;=0A= + }=0A= +=0A= + return true;=0A= +}=0A= +=0A= static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data,=0A= unsigned int size)=0A= {=0A= AspeedSBCState *s =3D ASPEED_SBC(opaque);=0A= + AspeedSBCClass *sc =3D ASPEED_SBC_GET_CLASS(s);=0A= =0A= addr >>=3D 2;=0A= =0A= @@ -244,6 +365,26 @@ static void aspeed_sbc_write(void *opaque, hwaddr addr= , uint64_t data,=0A= case R_CMD:=0A= aspeed_sbc_handle_command(opaque, data);=0A= return;=0A= + case R_SEC_TRIGGER:=0A= + if (data & RSA_CMD_TRIGGER) {=0A= + qemu_log_mask(LOG_UNIMP,=0A= + "%s: RSA is not supported\n", __func__);=0A= + }=0A= + if (data & ECDSA_CMD_TRIGGER) {=0A= + if (!sc->has_ecdsa) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: ECDSA is not supported\n", __func__);= =0A= + return;=0A= + }=0A= + s->regs[R_STATUS] &=3D ~(ECDSA_VERIFY_DONE | ECDSA_VERIFY_PASS= );=0A= + if (aspeed_sbc_ecdsa_verify(s)) {=0A= + s->regs[R_STATUS] |=3D ECDSA_VERIFY_PASS;=0A= + }=0A= + s->regs[R_STATUS] |=3D ECDSA_VERIFY_DONE;=0A= + trace_aspeed_sbc_ecdsa_verify(=0A= + (s->regs[R_STATUS] & ECDSA_VERIFY_PASS) ? "pass" : "fail")= ;=0A= + }=0A= + return;=0A= default:=0A= break;=0A= }=0A= diff --git a/hw/misc/trace-events b/hw/misc/trace-events=0A= index bbec0d2178..735d11d447 100644=0A= --- a/hw/misc/trace-events=0A= +++ b/hw/misc/trace-events=0A= @@ -95,6 +95,8 @@ aspeed_sbc_ignore_cmd(uint32_t cmd) "Ignoring command 0x%= " PRIx32=0A= aspeed_sbc_handle_cmd(uint32_t cmd, uint32_t addr, bool ret) "Handling com= mand 0x%" PRIx32 " for OTP addr 0x%" PRIx32 " Result: %d"=0A= aspeed_sbc_otp_read(uint32_t addr, uint32_t value) "OTP Memory read: addr = 0x%" PRIx32 " value 0x%" PRIx32=0A= aspeed_sbc_otp_prog(uint32_t addr, uint32_t value) "OTP Memory write: addr= 0x%" PRIx32 " value 0x%" PRIx32=0A= +aspeed_sbc_ecdsa_verify(const char *result) "ECDSA verify done: %s"=0A= +aspeed_sbc_ecdsa_hexdump(const char *desc, uint32_t offset, const char *s)= "%s: 0x%08x: %s"=0A= =0A= # aspeed_scu.c=0A= aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" P= RIx64 " of size %u: 0x%" PRIx32=0A= -- =0A= 2.53.0=0A=