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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b91c5790csm294645385e9.0.2026.09.01.02.53.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Sep 2026 02:53:51 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Zhao Liu , Peter Maydell , Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bibo Mao , Song Gao <17746591750@163.com>, Xianglai Li Subject: [PATCH v5 11/21] target/loongarch: Constify CPULoongArchState for various cpu_*() getters Date: Tue, 1 Sep 2026 11:52:17 +0200 Message-ID: <20260901095229.72018-12-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX4sqlTUuolIKJ zN7JkXDFrLoulhTPOUqx4YcuKOI74oAujChCQ09OPwzGPUugolDYivTiaZiXEWNQFRY1kD3q8+X 0hUXTjxwiDt2/LQlflFX9Gr9VVyZzFM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX0IfwnKEzQtjE PQ27t4oRZM2hbImImMLP9GOqP942BkLfpxce4dI9qJ10oHJ3ZKyz7QDXUHrz/2VWfAOGWuBwGD2 8z6krtKJOnvyVlto8FkArqR2Gkw79VVUg/50uehjL2ONkZInHmBcmPTRPaF0RNN6j1ZGVeJSdz7 E1Faikkg873LmLeeTSH9GkE2eCQMODPrFNr/9FuENgVnmEtuTmVQPLEJXw3Hsd5lUq2RRrN7Pky CTslY8lYmpYkQ2L5celqdNPqeaYUqlGY1HqpO3dNFRR4nmxVthGAaSb047T51FAf3hpKEz6nuQS QTXHOXoMPo/B9I6YsYsHpGcIE/hxayi+K6dbI17ZULtRJHaPE0iBNRP5iIjDMu4h+gHITvzgdJP MQBBHgqdzUgwqdM6/y/0Ra0kbGD+1swDIdMdsirbY08WsugcBxr6/LHRj8HgQgDY4g01ppV/5c9 XbjZpVE9Y+4wUU91Z/A== X-Proofpoint-GUID: w_Cy-gxA-XpggIzCKL7IBEebDrFhW-f1 X-Proofpoint-ORIG-GUID: w_Cy-gxA-XpggIzCKL7IBEebDrFhW-f1 X-Authority-Analysis: v=2.4 cv=QsNuG1yd c=1 sm=1 tr=0 ts=6a96a0b2 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=20KFwNOVAAAA:8 a=IBuu09U9_flyDEDmYOIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add the const qualifier to CPULoongArchState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Marc-André Lureau Reviewed-by: Bibo Mao --- target/loongarch/cpu.h | 6 +++--- target/loongarch/internals.h | 2 +- target/loongarch/cpu.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 97db3b453fe..ad8e7497279 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -486,7 +486,7 @@ struct LoongArchCPUClass { #define MMU_USER_IDX MMU_PLV_USER #define MMU_DA_IDX 4 -static inline CPUSysState *env_sys(CPULoongArchState *env) +static inline CPUSysState *env_sys(const CPULoongArchState *env) { return env->sys_state; } @@ -496,12 +496,12 @@ static inline void set_sys_state(CPULoongArchState *env, CPUSysState *sys) env->sys_state = sys; } -static inline bool is_la64(CPULoongArchState *env) +static inline bool is_la64(const CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; } -static inline bool is_va32(CPULoongArchState *env) +static inline bool is_va32(const CPULoongArchState *env) { /* VA32 if !LA64 or VA32L[1-3] */ bool va32 = !is_la64(env); diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 5e9a6c7bd65..a831507f439 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -39,7 +39,7 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu); uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env); +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env); #endif /* !CONFIG_USER_ONLY */ uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 7b601bd3728..3b3cbde882f 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -96,7 +96,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level) } /* Check if there is pending and not masked out interrupt */ -bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env) +bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env) { uint32_t pending; uint32_t status; -- 2.53.0