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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b9267c369sm237418685e9.3.2026.09.01.02.54.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Sep 2026 02:54:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Zhao Liu , Peter Maydell , Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v5 13/21] target/mips: Constify CPUMIPSState for various cpu_*() getters Date: Tue, 1 Sep 2026 11:52:19 +0200 Message-ID: <20260901095229.72018-14-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=beZbluPB c=1 sm=1 tr=0 ts=6a96a0c0 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=20KFwNOVAAAA:8 a=h4i2fRRWLofFFTjKLt8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX0NxJDhgslsbw 3l9OUL/qjD6X6ePgPenottyzf7GeQjvlnbMYFyYf7EzxScIOU5Yqnf8VD2BZROLDHHB771VGNG7 qVrklZGHKv3tWtG0217B/zvjAk4emrFAO0/TPdUX16XX+YxEGzYxFkRySobKIkjnHwNzrJx+oNv aRuQZqZ1ojP2FiuFb4eIW3rFSSl6kaGOnuxY1Nhr5LjQKDC4/owMBQZNGqNwch9TwHOJTPhAEhS 7km1/jklc4tb8D4TMRZfZ7dXLQ7EQT6Vy2ZsnV9BlDSA0Vc8aNxhuKQ7tnj8gIAii96CRwuPHZK d7ra/q77VU8LpY7h/AORHRmlE1T5Kapi5I5gGspmoGTIrzJ9apmc9VLp9QIs5fcWORPxEcOWKpO V3/WdDrYzvsWWB9m0tAYj57kSbB2mMu4PTKr+2FH8GScYv0qhcf6ufT8jg+UWnLYeaLBoghw5mj 18GwEG4SYRRzdxPBIpQ== X-Proofpoint-GUID: dfzobXR9Db-Mo-yD4xpE2w8To4TQ00Dn X-Proofpoint-ORIG-GUID: dfzobXR9Db-Mo-yD4xpE2w8To4TQ00Dn X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX4rlI7c9qkXh9 IhV2py2yFd6/BL7xMTvb4Y2PflyT8il3zT6Xz+xRlCUiLSDguWIj4uXcKYSdbsEniuetG9afCOT 10b9X8/Ppowl163uS0bEAWozZx/fflw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 malwarescore=0 spamscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add the const qualifier to CPUMIPSState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Marc-André Lureau --- target/mips/cpu.h | 8 ++++---- target/mips/internal.h | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 319147a948c..32549791a18 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1300,7 +1300,7 @@ static inline int hflags_mmu_index(uint32_t hflags) } } -static inline int mips_env_mmu_index(CPUMIPSState *env) +static inline int mips_env_mmu_index(const CPUMIPSState *env) { return hflags_mmu_index(env->hflags); } @@ -1372,19 +1372,19 @@ static inline bool ase_3d_available(const CPUMIPSState *env) } /* Check presence of MSA implementation */ -static inline bool ase_msa_available(CPUMIPSState *env) +static inline bool ase_msa_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MSAP); } /* Check presence of Loongson CSR instructions */ -static inline bool ase_lcsr_available(CPUMIPSState *env) +static inline bool ase_lcsr_available(const CPUMIPSState *env) { return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP); } /* Check presence of multi-threading ASE implementation */ -static inline bool ase_mt_available(CPUMIPSState *env) +static inline bool ase_mt_available(const CPUMIPSState *env) { return env->CP0_Config3 & (1 << CP0C3_MT); } diff --git a/target/mips/internal.h b/target/mips/internal.h index c5c286872eb..7dba22300b1 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -165,7 +165,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); extern const VMStateDescription vmstate_mips_cpu; -static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_enabled(const CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && !(env->CP0_Status & (1 << CP0St_EXL)) && @@ -180,7 +180,7 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) } /* Check if there is pending and not masked out interrupt */ -static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) +static inline bool cpu_mips_hw_interrupts_pending(const CPUMIPSState *env) { int32_t pending; int32_t status; @@ -247,9 +247,9 @@ static inline void restore_pamask(CPUMIPSState *env) } } -static inline int mips_vpe_active(CPUMIPSState *env) +static inline int mips_vpe_active(const CPUMIPSState *env) { - MIPSCPU *cpu = env_archcpu(env); + const MIPSCPU *cpu = env_archcpu(env); int active = 1; /* Check that the VPE is enabled. */ @@ -281,7 +281,7 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } -static inline int mips_vp_active(CPUMIPSState *env) +static inline int mips_vp_active(const CPUMIPSState *env) { CPUState *cs; -- 2.53.0