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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdce1e1ebsm56936285e9.14.2026.09.01.02.54.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Sep 2026 02:54:36 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Zhao Liu , Peter Maydell , Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH v5 17/21] target/sparc: Constify CPUSPARCState for various cpu_*() getters Date: Tue, 1 Sep 2026 11:52:23 +0200 Message-ID: <20260901095229.72018-18-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: aOqDCB1rwbIKqA44q4-WOu_OWjbkwVZx X-Authority-Analysis: v=2.4 cv=G9Ms1dk5 c=1 sm=1 tr=0 ts=6a96a0de cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=20KFwNOVAAAA:8 a=tlxghdvPRZsVr19qFskA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: aOqDCB1rwbIKqA44q4-WOu_OWjbkwVZx X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX3U9wNk0UZ2OF 0ZNNV+BCGJC+Jkt7g36jPeKtPpR12kljbdWAALqJCV41YbGUkPwnYHCfAVC0TUhcpjTypZQSCbX diHmRhe2hh4K0E7IHIc9nVeuiPEOsi8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfXyjfFhQX/0b8G OEGMfZTg7sw+9RiZRCw5abyi60Amps2/wyA46QveAqviCfEmqV7MogA/LjAg1FsDc1IzFdYFKbH a3QNp90W10S/lBhuNFj9d6Pq4Tq8Wga1JZBeJoHkwowuVFByRZZYZOFZ9kG0q1VMVSA7YtPabeN 2vWCrKX14yA5BaF4OWL7bJshPMa1KeWYeZ9lsXY47WsIB78+4CGKWrVUspsPYpIyqejxE3uNAjk vSr+PquHdh/hg22hMbGWh7sPC8CNQiB+Z27gt1tVF9w6N+p+EM72dDoBvI6KIqaPGU+gzNSQ6k2 XdbK1PRfHq8+v4rJMOkayHKRu9uqL0Rv+/BSC2TRDaqF8O8D7DmnRwBzi1GJ7xxMCHct1/aZbZP 5e6GDZYFTzYzgtF6zZkssQBuuqPWIA9eB8qtJ07yfUbODn0n/utRv1p7LpBqmtVyMKnK6Th/tlt IjWvvPQgW84V7PuZJDA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 impostorscore=0 spamscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Add the const qualifier to CPUSPARCState when the argument is accessed without modification. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Marc-André Lureau --- target/sparc/cpu.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5f583ed9de2..31a16c2af03 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -680,28 +680,28 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, #endif #if defined (TARGET_SPARC64) -static inline int cpu_has_hypervisor(CPUSPARCState *env1) +static inline int cpu_has_hypervisor(const CPUSPARCState *env1) { return env1->def.features & CPU_FEATURE_HYPV; } -static inline int cpu_hypervisor_mode(CPUSPARCState *env1) +static inline int cpu_hypervisor_mode(const CPUSPARCState *env1) { return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); } -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->pstate & PS_PRIV; } #else -static inline int cpu_supervisor_mode(CPUSPARCState *env1) +static inline int cpu_supervisor_mode(const CPUSPARCState *env1) { return env1->psrs; } #endif -static inline int cpu_interrupts_enabled(CPUSPARCState *env1) +static inline int cpu_interrupts_enabled(const CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) if (env1->psret != 0) @@ -715,7 +715,7 @@ static inline int cpu_interrupts_enabled(CPUSPARCState *env1) return 0; } -static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) +static inline int cpu_pil_allowed(const CPUSPARCState *env1, int pil) { #if !defined(TARGET_SPARC64) /* level 15 is non-maskable on sparc v8 */ -- 2.53.0