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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48442d37ce3sm3754006f8f.8.2026.09.01.02.54.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Sep 2026 02:54:58 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Zhao Liu , Peter Maydell , Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Rolnik , Brian Cain , Pierrick Bouvier , Helge Deller , Song Gao <17746591750@163.com>, Bibo Mao , Xianglai Li , Laurent Vivier , "Edgar E. Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Cornelia Huck , Eric Farman , Matthew Rosato , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 20/21] cpus: Constify @cpu in SysemuCPUOps::has_work() handler Date: Tue, 1 Sep 2026 11:52:26 +0200 Message-ID: <20260901095229.72018-21-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=b9qCJNGx c=1 sm=1 tr=0 ts=6a96a0f5 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=cM1bI5kxBi4gRGPUlTgA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX2G/rxXCERIJJ XF2ZrWyYiGUAEVihf7TAfLV8oY03SIPdoiwxxABl/ztlETQuC+3XEigQvl9dFJtjQD3iMxn/Be7 8xp5SW7vNfxLFXBppjARN35l2im7tUcN0fjuhXadpOUXmbiLliyzbtE6zXIgWWu/4IL9p2YO5Op 1V9iSUACoIGo4XVNx46ZS9sn+z3zGLbDbsapmb5MXHO72Zi1WEUsDAQQniI3JpB3+PQ5yfupj8Y l7whfyrWKxiV0VKiG0B7aXi328y6K0hXY6Pwvc/hqmbefj6OSdIbOx5yc7gyJ5DATU8VWZvPRvO i6LmB/gpw475UiWYfXzhjlWnXAkoy1L6RbW/pg9zAfomgx2ftLtVLwl95uqGhIaB742P3a50mdl ybiyxqJx4GGJRq8lgRuJSOFe2Ky4vkPHOXlpv32BKqJWgUqZJJ0gCkWl0IvO3qKsH3YWsLviENI lxtrWrrfuEwYvT6supA== X-Proofpoint-GUID: NEGu0s-ZLSJG7cKRCjZUbRbJbuC4mRFo X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX0j+pzX6FvQRK nIM6NT2klzpWyd0RJ0kqQvIG5TY5ZlkeD8GJX9Gvt6u0yEv/SwZjTRkcdQORUf7L0pXG1NU3iu5 Z3USxwsM7/57sBB6/FmkpdGxF08336M= X-Proofpoint-ORIG-GUID: NEGu0s-ZLSJG7cKRCjZUbRbJbuC4mRFo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org All functions called by target has_work() handler take a const @cpu argument. We can now fulfill the comment added in commit c2804566f6 ("target/arm: do not clear halting reason in has_work helper"), qualifying the handler const to denote its idempotency. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/sysemu-cpu-ops.h | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 3 ++- target/hexagon/cpu.c | 4 ++-- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 ++-- target/or1k/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/cpu.c | 5 ++--- target/rx/cpu.c | 2 +- target/s390x/cpu-system.c | 4 ++-- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 4 ++-- 20 files changed, 28 insertions(+), 28 deletions(-) diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h index 9a45596169a..095bdcd997a 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -19,10 +19,10 @@ typedef struct SysemuCPUOps { /** * @has_work: Callback for checking if there is work to do. * - * This function should be idempotent (i.e. not change state) as + * This function is idempotent (i.e. not change state) as * it will likely be queried multiple times before a CPU resumes. */ - bool (*has_work)(CPUState *cpu); /* MANDATORY NON-NULL */ + bool (*has_work)(const CPUState *cpu); /* MANDATORY NON-NULL */ /** * @get_memory_mapping: Callback for obtaining the memory mappings. */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 7d1d036e1d3..21d4f8ac23b 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -77,7 +77,7 @@ static void alpha_restore_state_to_opc(CPUState *cs, } #ifndef CONFIG_USER_ONLY -static bool alpha_cpu_has_work(CPUState *cs) +static bool alpha_cpu_has_work(const CPUState *cs) { /* Here we are checking to see if the CPU should wake up from HALT. We will have gotten into this state only for WTINT from PALmode. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9761bb173c1..ba66359d410 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch) * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here * unconditionally. */ -static bool arm_cpu_has_work(CPUState *cs) +static bool arm_cpu_has_work(const CPUState *cs) { - ARMCPU *cpu = ARM_CPU(cs); + const ARMCPU *cpu = ARM_CPU(cs); /* * Only another PSCI call can wake the CPU up in which case the diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a01e6fa4751..a96bef46ff1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "exec/translation-block.h" #include "system/address-spaces.h" +#include "hw/core/cpu.h" #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" @@ -43,7 +44,7 @@ static vaddr avr_cpu_get_pc(CPUState *cs) return cpu->env.pc_w * 2; } -static bool avr_cpu_has_work(CPUState *cs) +static bool avr_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET) && cpu_interrupts_enabled(cpu_env(cs)); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 4cc6bd67c28..868aef0cde4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -364,9 +364,9 @@ bool hexagon_thread_is_enabled(const CPUHexagonState *env) return E_bit; } -static bool hexagon_cpu_has_work(CPUState *cs) +static bool hexagon_cpu_has_work(const CPUState *cs) { - CPUHexagonState *env = cpu_env(cs); + const CPUHexagonState *env = cpu_env(cs); return hexagon_thread_is_enabled(env) && (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7b1309a7c38..dbf58466c24 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -134,7 +134,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, } #ifndef CONFIG_USER_ONLY -static bool hppa_cpu_has_work(CPUState *cs) +static bool hppa_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1fc02cf94e6..0606ac16664 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10638,7 +10638,7 @@ int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request) return 0; } -static bool x86_cpu_has_work(CPUState *cs) +static bool x86_cpu_has_work(const CPUState *cs) { return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; } diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 3b3cbde882f..3fc208e44f8 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -110,7 +110,7 @@ bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env) #endif #ifndef CONFIG_USER_ONLY -static bool loongarch_cpu_has_work(CPUState *cs) +static bool loongarch_cpu_has_work(const CPUState *cs) { bool has_work = false; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 523694d8fbf..da3681fab1f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_restore_state_to_opc(CPUState *cs, } #ifndef CONFIG_USER_ONLY -static bool m68k_cpu_has_work(CPUState *cs) +static bool m68k_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6013a8def8e..d1d2f0ec7e3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -127,7 +127,7 @@ static void mb_restore_state_to_opc(CPUState *cs, } #ifndef CONFIG_USER_ONLY -static bool mb_cpu_has_work(CPUState *cs) +static bool mb_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c069aa1c0b7..0f39f8fe0a5 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -134,9 +134,9 @@ static vaddr mips_cpu_get_pc(CPUState *cs) } #if !defined(CONFIG_USER_ONLY) -static bool mips_cpu_has_work(CPUState *cs) +static bool mips_cpu_has_work(const CPUState *cs) { - CPUMIPSState *env = cpu_env(cs); + const CPUMIPSState *env = cpu_env(cs); bool has_work = false; /* diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 42d9351b6d7..10b13ae69cd 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -76,7 +76,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs, } #ifndef CONFIG_USER_ONLY -static bool openrisc_cpu_has_work(CPUState *cs) +static bool openrisc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER); } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ef59c56f416..c72a7168a23 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7222,7 +7222,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) #endif /* CONFIG_TCG */ #ifndef CONFIG_USER_ONLY -static bool ppc_cpu_has_work(CPUState *cs) +static bool ppc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6004da4ac33..5c16c52e010 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -953,10 +953,9 @@ int riscv_cpu_vsirq_pending(const CPURISCVState *env) (irqs | irqs_f_vs), env->hviprio); } -static bool riscv_cpu_has_work(CPUState *cs) +static bool riscv_cpu_has_work(const CPUState *cs) { - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; + const CPURISCVState *env = cpu_env(cs); /* * Definition of the WFI instruction requires it to ignore the privilege * mode and delegation registers, but respect individual enables diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 69946928995..dfa09a85bce 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -73,7 +73,7 @@ static void rx_restore_state_to_opc(CPUState *cs, cpu->env.pc = data[0]; } -static bool rx_cpu_has_work(CPUState *cs) +static bool rx_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index 84faceb3338..3a0ff46e144 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -39,9 +39,9 @@ #include "system/tcg.h" #include "hw/core/sysemu-cpu-ops.h" -static bool s390_cpu_has_work(CPUState *cs) +static bool s390_cpu_has_work(const CPUState *cs) { - S390CPU *cpu = S390_CPU(cs); + const S390CPU *cpu = S390_CPU(cs); /* STOPPED cpus can never wake up */ if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD && diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 55c73a1da35..b0ed356d0f7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -107,7 +107,7 @@ static bool superh_io_recompile_replay_branch(CPUState *cs, return false; } -static bool superh_cpu_has_work(CPUState *cs) +static bool superh_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 2baa5036871..8dd9b0d5ee3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -783,7 +783,7 @@ static void sparc_restore_state_to_opc(CPUState *cs, } #ifndef CONFIG_USER_ONLY -static bool sparc_cpu_has_work(CPUState *cs) +static bool sparc_cpu_has_work(const CPUState *cs) { return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(cpu_env(cs)); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 82b56c3cd56..357f3737053 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -111,7 +111,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetType type) cpu_state_reset(cpu_env(cs)); } -static bool tricore_cpu_has_work(CPUState *cs) +static bool tricore_cpu_has_work(const CPUState *cs) { /* Interrupts are not implemented */ return true; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c8bd4b5fb..1b299568776 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -140,9 +140,9 @@ static void xtensa_restore_state_to_opc(CPUState *cs, } #ifndef CONFIG_USER_ONLY -static bool xtensa_cpu_has_work(CPUState *cs) +static bool xtensa_cpu_has_work(const CPUState *cs) { - CPUXtensaState *env = cpu_env(cs); + const CPUXtensaState *env = cpu_env(cs); return !env->runstall && env->pending_irq_level; } -- 2.53.0