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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdce1e1ebsm56962825e9.14.2026.09.01.02.55.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Sep 2026 02:55:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Zhao Liu , Peter Maydell , Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Rolnik , Brian Cain , Pierrick Bouvier , Helge Deller , Song Gao <17746591750@163.com>, Bibo Mao , Xianglai Li , Laurent Vivier , "Edgar E. Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Chinmay Rath , Nicholas Piggin , Glenn Miles , Harsh Prateek Bora , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Cornelia Huck , Eric Farman , Matthew Rosato , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 21/21] accel/tcg: Constify @cpu in cpu_mmu_index() and TCGCPUOps handlers Date: Tue, 1 Sep 2026 11:52:27 +0200 Message-ID: <20260901095229.72018-22-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=f6p4wuyM c=1 sm=1 tr=0 ts=6a96a0ff cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=g_x95mRnQQNavG41apYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX5aS2/Rz0fhmD AiwpTx+hY8aNpl34Old9eq4IXSnAYAr29FX3F2DsmLz8M/WsT5evwesoOXa7BCiOZLjbODt4A7X cMVbKRxkJzlRpT5AlzpkS0ah5vm1IS5vy70CAhqAGAr6R/4u21o8cXvhut9z+tjOo0ssEALgQDp 5vYoUQxXpCejiwAzjRDjgZCfZvU8Azxzzb3nTQLrIx+7cMZAGYMXbCW9iYNIE7YGS1Ffp5LRNHA sk6DUPcCjaUNqD2vNm2pGeIzxY0VDG8QXP/sUj1vvWuKLlSqd/BidWPJ7waVkKZK+0DkFDJkkLz JyJRWsu8eY3xfz5YUKIutEXQpkOe3V2dLaiJNl8SE4ZGvBAVzuYZGL9QN2YFGq0b0z9rBIGKWy/ bWuWpMGT9vW/r1mQJUDWQaBh9YM6ELsBqyU/lBZZWqOXCyYTPyABEdAre4oyAaNzqcOCnjZXSR9 f3tO6CWTHOE2d4V3/rA== X-Proofpoint-ORIG-GUID: uVKceSmYN_xAoWmeDL1ifmPhM_VHIhlR X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX9EcTbmAwx4qB 6DTMgv0Sips2gux6G+d2FzF/6Ec00CDUbQWkzdLLBCPUokflJWLlx1JpFmBhHG++l/vXgewRM9/ RZYyESZ/UPwVJXdk0pjI3BoR6znAzhA= X-Proofpoint-GUID: uVKceSmYN_xAoWmeDL1ifmPhM_VHIhlR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 priorityscore=1501 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All functions called by cpu_mmu_index() take a const @cpu argument. Propagate the constness to the caller (CPU state should not mutate when resolving the MMU index of the current translation regime). Signed-off-by: Philippe Mathieu-Daudé --- include/accel/tcg/cpu-mmu-index.h | 2 +- include/accel/tcg/cpu-ops.h | 2 +- target/alpha/cpu.h | 2 +- target/arm/internals.h | 4 ++-- target/i386/tcg/tcg-cpu.h | 2 +- target/ppc/cpu.h | 2 +- target/s390x/cpu.h | 2 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 6 +++--- target/hppa/cpu.c | 4 ++-- target/i386/tcg/tcg-cpu.c | 6 +++--- target/loongarch/tcg/tcg_cpu.c | 4 ++-- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 6 +++--- target/mips/cpu.c | 2 +- target/or1k/cpu.c | 4 ++-- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 4 ++-- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 26 files changed, 38 insertions(+), 38 deletions(-) diff --git a/include/accel/tcg/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-index.h index e0fb6ef91c8..01152075372 100644 --- a/include/accel/tcg/cpu-mmu-index.h +++ b/include/accel/tcg/cpu-mmu-index.h @@ -30,7 +30,7 @@ * Return the core mmu index for the current translation regime. * This function is used by generic TCG code paths. */ -static inline int cpu_mmu_index(CPUState *cs, bool ifetch) +static inline int cpu_mmu_index(const CPUState *cs, bool ifetch) { #ifdef COMPILING_PER_TARGET # ifdef CONFIG_USER_ONLY diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h index a88cc4dc572..69d7ec29115 100644 --- a/include/accel/tcg/cpu-ops.h +++ b/include/accel/tcg/cpu-ops.h @@ -102,7 +102,7 @@ struct TCGCPUOps { void (*debug_excp_handler)(CPUState *cpu); /** @mmu_index: Callback for choosing softmmu mmu index */ - int (*mmu_index)(CPUState *cpu, bool ifetch); + int (*mmu_index)(const CPUState *cpu, bool ifetch); #ifdef CONFIG_USER_ONLY /** diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 378bd96d941..1c9f9fce20b 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -383,7 +383,7 @@ enum { #define TB_FLAG_UNALIGN (1u << 1) -static inline int alpha_env_mmu_index(CPUAlphaState *env) +static inline int alpha_env_mmu_index(const CPUAlphaState *env) { int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; if (env->flags & ENV_FLAG_PAL_MODE) { diff --git a/target/arm/internals.h b/target/arm/internals.h index f1a80c890ee..d582cefcfa4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -55,7 +55,7 @@ static inline MemOp mo_endian(const CPUARMState *env) return EX_TBFLAG_ANY(env->hflags, BE_DATA) ? MO_BE : MO_LE; } -static inline int arm_env_mmu_index(CPUARMState *env) +static inline int arm_env_mmu_index(const CPUARMState *env) { return EX_TBFLAG_ANY(env->hflags, MMUIDX); } @@ -431,7 +431,7 @@ void arm_restore_state_to_opc(CPUState *cs, #ifdef CONFIG_TCG TCGTBCPUState arm_get_tb_cpu_state(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -int arm_cpu_mmu_index(CPUState *cs, bool ifetch); +int arm_cpu_mmu_index(const CPUState *cs, bool ifetch); #endif /* CONFIG_TCG */ typedef enum ARMFPRounding { diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h index 85bcd61678f..1127861e337 100644 --- a/target/i386/tcg/tcg-cpu.h +++ b/target/i386/tcg/tcg-cpu.h @@ -82,6 +82,6 @@ extern const TCGCPUOps x86_tcg_ops; bool tcg_cpu_realizefn(CPUState *cs, Error **errp); -int x86_mmu_index_pl(CPUX86State *env, unsigned pl); +int x86_mmu_index_pl(const CPUX86State *env, unsigned pl); #endif /* TCG_CPU_H */ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3fb51bbeb82..56264752c1b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1736,7 +1736,7 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); /* MMU modes definitions */ #define MMU_USER_IDX 0 -static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch) +static inline int ppc_env_mmu_index(const CPUPPCState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 998bbb0d7ff..cd5f9256b24 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -373,7 +373,7 @@ QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT); #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 -static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) +static inline int s390x_env_mmu_index(const CPUS390XState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return MMU_USER_IDX; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 21d4f8ac23b..3bf88702dc1 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -93,7 +93,7 @@ static bool alpha_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) +static int alpha_cpu_mmu_index(const CPUState *cs, bool ifetch) { return alpha_env_mmu_index(cpu_env(cs)); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ba66359d410..63ef00735ca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -126,7 +126,7 @@ void arm_restore_state_to_opc(CPUState *cs, } } -int arm_cpu_mmu_index(CPUState *cs, bool ifetch) +int arm_cpu_mmu_index(const CPUState *cs, bool ifetch) { return arm_env_mmu_index(cpu_env(cs)); } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a96bef46ff1..24a5a9debc9 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -50,7 +50,7 @@ static bool avr_cpu_has_work(const CPUState *cs) && cpu_interrupts_enabled(cpu_env(cs)); } -static int avr_cpu_mmu_index(CPUState *cs, bool ifetch) +static int avr_cpu_mmu_index(const CPUState *cs, bool ifetch) { return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 868aef0cde4..2bc58fc6305 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -482,11 +482,11 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } -static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch) +static int hexagon_cpu_mmu_index(const CPUState *cs, bool ifetch) { #ifndef CONFIG_USER_ONLY - CPUHexagonState *env = cpu_env(cs); - HexagonCPU *cpu = HEXAGON_CPU(cs); + const CPUHexagonState *env = cpu_env(cs); + const HexagonCPU *cpu = HEXAGON_CPU(cs); int cpu_mode; BQL_LOCK_GUARD(); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index dbf58466c24..ec351302406 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -140,9 +140,9 @@ static bool hppa_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) +static int hppa_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUHPPAState *env = cpu_env(cs); + const CPUHPPAState *env = cpu_env(cs); if (env->psw & (ifetch ? PSW_C : PSW_D)) { return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e4fc212aca5..da1498ee45d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -114,7 +114,7 @@ static void x86_restore_state_to_opc(CPUState *cs, } } -int x86_mmu_index_pl(CPUX86State *env, unsigned pl) +int x86_mmu_index_pl(const CPUX86State *env, unsigned pl) { int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; int mmu_index_base = @@ -125,9 +125,9 @@ int x86_mmu_index_pl(CPUX86State *env, unsigned pl) return mmu_index_base + mmu_index_32; } -static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) +static int x86_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUX86State *env = cpu_env(cs); + const CPUX86State *env = cpu_env(cs); return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); } diff --git a/target/loongarch/tcg/tcg_cpu.c b/target/loongarch/tcg/tcg_cpu.c index 7ea2a1eb933..a26233d5eed 100644 --- a/target/loongarch/tcg/tcg_cpu.c +++ b/target/loongarch/tcg/tcg_cpu.c @@ -301,9 +301,9 @@ static void loongarch_restore_state_to_opc(CPUState *cs, set_pc(cpu_env(cs), data[0]); } -static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) +static int loongarch_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPULoongArchState *env = cpu_env(cs); + const CPULoongArchState *env = cpu_env(cs); CPUSysState *sys = env_sys(env); if (FIELD_EX64(sys->CSR_CRMD, CSR_CRMD, PG)) { diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index da3681fab1f..f1fd2e6f14d 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -82,7 +82,7 @@ static bool m68k_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int m68k_cpu_mmu_index(CPUState *cs, bool ifetch) +static int m68k_cpu_mmu_index(const CPUState *cs, bool ifetch) { return cpu_env(cs)->sr & SR_S ? MMU_KERNEL_IDX : MMU_USER_IDX; } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index d1d2f0ec7e3..524175d2236 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -133,10 +133,10 @@ static bool mb_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int mb_cpu_mmu_index(CPUState *cs, bool ifetch) +static int mb_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUMBState *env = cpu_env(cs); - MicroBlazeCPU *cpu = env_archcpu(env); + const CPUMBState *env = cpu_env(cs); + const MicroBlazeCPU *cpu = env_archcpu(env); /* Are we in nommu mode?. */ if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0f39f8fe0a5..a428176d9e8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -671,7 +671,7 @@ static const Property mips_cpu_properties[] = { #ifdef CONFIG_TCG #include "accel/tcg/cpu-ops.h" -static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) +static int mips_cpu_mmu_index(const CPUState *cs, bool ifunc) { return mips_env_mmu_index(cpu_env(cs)); } diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c index 10b13ae69cd..c9ab5c0f1c1 100644 --- a/target/or1k/cpu.c +++ b/target/or1k/cpu.c @@ -82,9 +82,9 @@ static bool openrisc_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int openrisc_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUOpenRISCState *env = cpu_env(cs); + const CPUOpenRISCState *env = cpu_env(cs); if (env->sr & (ifetch ? SR_IME : SR_DME)) { /* The mmu is enabled; test supervisor state. */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c72a7168a23..a33a074b796 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7215,7 +7215,7 @@ static void ppc_restore_state_to_opc(CPUState *cs, cpu->env.nip = data[0]; } -static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int ppc_cpu_mmu_index(const CPUState *cs, bool ifetch) { return ppc_env_mmu_index(cpu_env(cs), ifetch); } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index cd303660f1f..a0210ca50e3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -95,7 +95,7 @@ static const char *cpu_priv_ver_to_str(int priv_ver) return priv_spec_str; } -static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) +static int riscv_cpu_mmu_index(const CPUState *cs, bool ifetch) { return riscv_env_mmu_index(cpu_env(cs), ifetch); } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index dfa09a85bce..c5dfba8976a 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -78,7 +78,7 @@ static bool rx_cpu_has_work(const CPUState *cs) return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } -static int rx_cpu_mmu_index(CPUState *cs, bool ifunc) +static int rx_cpu_mmu_index(const CPUState *cs, bool ifunc) { return 0; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index c34f4b23472..a043f1e7920 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -311,7 +311,7 @@ static const Property s390x_cpu_properties[] = { #include "accel/tcg/cpu-ops.h" #include "tcg/tcg_s390x.h" -static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch) +static int s390x_cpu_mmu_index(const CPUState *cs, bool ifetch) { return s390x_env_mmu_index(cpu_env(cs), ifetch); } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index b0ed356d0f7..f8b33844d2a 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -113,9 +113,9 @@ static bool superh_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sh4_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUSH4State *env = cpu_env(cs); + const CPUSH4State *env = cpu_env(cs); /* * The instruction in a RTE delay slot is fetched in privileged mode, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 8dd9b0d5ee3..f1ae16c91e9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -790,9 +790,9 @@ static bool sparc_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch) +static int sparc_cpu_mmu_index(const CPUState *cs, bool ifetch) { - CPUSPARCState *env = cpu_env(cs); + const CPUSPARCState *env = cpu_env(cs); #ifndef TARGET_SPARC64 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 357f3737053..09d4270df60 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -117,7 +117,7 @@ static bool tricore_cpu_has_work(const CPUState *cs) return true; } -static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch) +static int tricore_cpu_mmu_index(const CPUState *cs, bool ifetch) { return 0; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 1b299568776..8cf973632e7 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -148,7 +148,7 @@ static bool xtensa_cpu_has_work(const CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int xtensa_cpu_mmu_index(CPUState *cs, bool ifetch) +static int xtensa_cpu_mmu_index(const CPUState *cs, bool ifetch) { return xtensa_get_cring(cpu_env(cs)); } -- 2.53.0