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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b91c9cf95sm262624555e9.1.2026.09.01.02.53.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 01 Sep 2026 02:53:29 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Zhao Liu , Peter Maydell , Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Brian Cain , Pierrick Bouvier Subject: [PATCH v5 08/21] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Date: Tue, 1 Sep 2026 11:52:14 +0200 Message-ID: <20260901095229.72018-9-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901095229.72018-1-philmd@oss.qualcomm.com> References: <20260901095229.72018-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=OcyoyBTY c=1 sm=1 tr=0 ts=6a96a09b cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=20KFwNOVAAAA:8 a=XxrlQHdRtCO5bKJNttYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: nXYDj5RprLaRtoNSZfqOGrowVWOKE4cj X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfX9xbCwQXLYfTa bgvXcoYmJcThzMkEEf1+XgaJarRW566lVkrbcxPAeaIxd61c64mdQp90ToHM4C0Hgnf5AVDBlUj /CCAvgVUNPh+WQdXmHlSaSzLNCByb2E= X-Proofpoint-GUID: nXYDj5RprLaRtoNSZfqOGrowVWOKE4cj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAxMDA4NyBTYWx0ZWRfXyaODwexOQYYw 41N6x2GaxdIkR50Wu6XXBlE2GzVqzvXCIhjSSo4VTkAIvyiAtkOdMccmEPtHhUgGyDV7K4RZ2Wt v0R7h+2BV7UG7MJpRk24IET3uOaHUnaeVfxMWowR8BwcPGlnSNyjtm6Cq7VtKeaXWl+Ip9zeVmr ul3iXqRPFjDaGRzfYChLkzxz8JrvyxGC67YGR/s4XEs6SDmL/wUCL96Xc4uGUaRnRcAe3xwabzJ Rhs1R7dO1d8HIfSAyZ6rXfrQznUmWogjy+hgkufxG6qLGRJ9ecDzJf7vzwZFXOncfDukGRmpSdD jss8xxZOaOf2WNfW3/iU+Z8nfFXv8r5ldLm4GGCSAeJ0HucJIi+kXg6UwbigDvG7wBkU1BeE5wG eDnPjFheTzr+mXkGI73ZIrkh1k2wqshbhmrsn/RKwjW+MjUSgOhaHGaM6TKwWjfVexxfxq8cs1x UaC88K7g83T3JGr/FNA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-01_02,2026-08-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609010087 Received-SPF: pass client-ip=205.220.168.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org @env argument is accessed without modification in hexagon_thread_is_enabled(), qualify it as const. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Marc-André Lureau Reviewed-by: Brian Cain --- target/hexagon/cpu.h | 2 +- target/hexagon/cpu_helper.h | 4 ++-- target/hexagon/cpu.c | 4 ++-- target/hexagon/cpu_helper.c | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c50fbb3f72a..e4f120eda17 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -216,7 +216,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, * @return true if the @a thread_env hardware thread is * not stopped. */ -bool hexagon_thread_is_enabled(CPUHexagonState *thread_env); +bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); void hexagon_cpu_soft_reset(CPUHexagonState *env); #endif diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index d1767503156..a669091a89d 100644 --- a/target/hexagon/cpu_helper.h +++ b/target/hexagon/cpu_helper.h @@ -9,8 +9,8 @@ uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index); void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old); -int get_cpu_mode(CPUHexagonState *env); -int get_exe_mode(CPUHexagonState *env); +int get_cpu_mode(const CPUHexagonState *env); +int get_exe_mode(const CPUHexagonState *env); void clear_wait_mode(CPUHexagonState *env); void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause); void hexagon_start_threads(CPUHexagonState *env, uint32_t mask); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 9765716b516..4cc6bd67c28 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -345,9 +345,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs, } #ifndef CONFIG_USER_ONLY -bool hexagon_thread_is_enabled(CPUHexagonState *env) +bool hexagon_thread_is_enabled(const CPUHexagonState *env) { - HexagonCPU *cpu = env_archcpu(env); + const HexagonCPU *cpu = env_archcpu(env); uint32_t modectl; uint32_t thread_enabled_mask; bool E_bit; diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 64c5746c6d9..610e29a0503 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -212,9 +212,9 @@ void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause) } -int get_exe_mode(CPUHexagonState *env) +int get_exe_mode(const CPUHexagonState *env) { - HexagonCPU *cpu; + const HexagonCPU *cpu; uint32_t modectl, thread_enabled_mask, thread_wait_mask; uint32_t isdbst, debugmode; bool E_bit, W_bit, D_bit; @@ -384,7 +384,7 @@ static int sys_in_user_mode_ssr(uint32_t ssr) return 0; } -int get_cpu_mode(CPUHexagonState *env) +int get_cpu_mode(const CPUHexagonState *env) { uint32_t ssr = env->t_sreg[HEX_SREG_SSR]; -- 2.53.0