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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JZxPbFADjlrl2s9SgzyrkgheC8j8JE7MGf++74eER4v7zJrh2Ta64u2eqGjRkcnh809UwplYboaFesOrlsVh5V+VHHXvysesID8cAZ4A74pN1GOnIiQ3OhdJ7N/TYNRmhvB91BjH2fdcec0HNqG16eC1LyRoGM5INf9wdA4B14N0oC0NqKkoa+gtPcW6y9RezbsVTUOftF3y+jZuzlk3tADgxE4Hg1SxWhpZug1Glj8KpeRxtm9S5mBfrmmg0MMsnAm0vIg+jcsEHxglvwW+BHYHw/XNiovOXUHjDzkR57y3aNRXReheZOiQHqy6WuyyhMoWr53JLQlssyxg5OGpz694qceGtchqGCI3EuxBz4ET8RGZpBOoSzgtRyQiKqkOObR087qIh8lab1PFtdXXNur2ARE7x9PGzkcdhOolCIGpQDtpfHmNeC3JyXg1Qi41 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2026 20:11:04.6369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4456e3d2-1f85-4768-ca00-08df086526df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4232 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" It's only used for GART TLB flushes so rename it and remove additional parameters that are never used. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 ++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 4 ++-- 3 files changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index c4c21dbbbdbf8..0db997c8fa03a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -502,7 +502,7 @@ void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) up_read(&adev->reset_domain->sem); } for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) - amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0); + amdgpu_gmc_flush_gpu_tlb_gart(adev, i); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 2f6d20c00ce29..6af4ed2170b06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -714,8 +714,8 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) return 0; } -void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, - uint32_t vmhub, uint32_t flush_type) +void amdgpu_gmc_flush_gpu_tlb_gart(struct amdgpu_device *adev, + uint32_t vmhub) { struct amdgpu_ring *ring; struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; @@ -725,7 +725,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); - if (!hub->sdma_invalidation_workaround || vmid || + if (!hub->sdma_invalidation_workaround || !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || !ring->sched.ready) { /* @@ -736,15 +736,11 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, return; if (adev->gmc.flush_tlb_needs_extra_type_2) - adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, vmhub, 2); - if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2) - adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, - vmhub, 0); - - adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, vmhub, - flush_type); + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, vmhub, + 0); up_read(&adev->reset_domain->sem); return; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index f8f4df37d5805..23954e3180a8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -441,8 +441,8 @@ int amdgpu_gmc_handle_retry_fault(struct amdgpu_device *adev, bool write_fault); int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); -void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, - uint32_t vmhub, uint32_t flush_type); +void amdgpu_gmc_flush_gpu_tlb_gart(struct amdgpu_device *adev, + uint32_t vmhub); int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst); -- 2.55.0