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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UwnMzMpAw76E/0NfLjt71J0Q1u18lpx9LlTGdPYL3tWiq4h4Ke6Jb3i4o+gkqyahe8ZhuHaEE8xla6IcvZ+Jt+wArfZdsFGfkiTxzEhkSBPECOdz05wVpchKBBoC/qtmW6j/JyWfxHLUG/l0ruiKkWuZ9XdUzo2IrqmQHK+E1Ry1K85XcWrDx7ybtImP+yeSnlKzfO+1O7Lefw/yPeR1yVucXm9vXxj8eDY7VeNgz72WFkPwwfr1V6jClbzFTUTNj/EbHIU3u5Z0tPF9MF+b8Qm/9x0snZts5Ft7eebAUaMyD1VOZrWfhzxglL/g7q3CyAk0X2crR4EbB4i2W+aZcHhEoO2Wq62F6nwcbL+0LOcjMyoKZY0PAHvA2Q/aFhmSIixV8knu+Gcy8Egm+4CUDIGYeF9uO+W5bnyJGKY/LucLiD2eQpdIhS4ZQCVpMnpf X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2026 20:10:58.3665 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cf6dbd8-3230-46ff-b909-08df08652329 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFE494AA682 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Plumb the invalidation method into amdgpu_gmc_flush_gpu_tlb_gart(). Keep the current behavior. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 6af4ed2170b06..779f9b0974d2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -719,15 +719,25 @@ void amdgpu_gmc_flush_gpu_tlb_gart(struct amdgpu_device *adev, { struct amdgpu_ring *ring; struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; + bool use_mmio; struct dma_fence *fence; struct amdgpu_job *job; int r; ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); - if (!hub->sdma_invalidation_workaround || - !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || - !ring->sched.ready) { + switch (adev->gmc.gart_inv_method) { + case AMDGPU_TLB_INV_METHOD_MMIO: + default: + use_mmio = !hub->sdma_invalidation_workaround; + break; + case AMDGPU_TLB_INV_METHOD_SDMA: + use_mmio = false; + break; + } + + if (!adev->mman.buffer_funcs_enabled || + !adev->ib_pool_ready || !ring->sched.ready || use_mmio) { /* * A GPU reset should flush all TLBs anyway, so no need to do * this while one is ongoing. -- 2.55.0