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Tue, 1 Sep 2026 15:10:57 -0500 From: Alex Deucher To: , CC: Alex Deucher Subject: [PATCH 19/31] drm/amdgpu: uplevel reset check in amdgpu_gmc_flush_gpu_tlb_gart() Date: Tue, 1 Sep 2026 16:10:22 -0400 Message-ID: <20260901201034.2960437-20-alexander.deucher@amd.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260901201034.2960437-1-alexander.deucher@amd.com> References: <20260901201034.2960437-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022571:EE_|CY8PR12MB7563:EE_ X-MS-Office365-Filtering-Correlation-Id: 98cd1a9d-b74b-4a75-5c50-08df086526e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700016|1800799024|23010399003|376014|22082099003|18002099003|56012099006|10067099003|11063799006; X-Microsoft-Antispam-Message-Info: R5Tt6/EfWuI2qVy14rOQwajiz/43CubummghwaRKH+5NafBXdkD/biR0J8yGUGFxCvyurMeWwi9tuz71DH2m24PxZ0h7BKDt/u0diKLXLB4SN5df8GdiC9gmbqPYN1geqIX4EUJvCUuOY+X4dN6KyWEXVjBUwt+y8EApoALnKOaWIjfwHsyz//OjNMjsBjIsERL6fNrwsimrdRZeTj6JQt6sFWUF+OYsu3xgYk306eL93mMr8HfNcehKQxx4tPIoPn8iBpfWzFdDiGilv3E2iQog3Jfw6L8lREK7OwcRKRRfrpxk2kgvBacQLjHwTzG28SIwr3Znp/4y6e/eVUPYHJurNNxC7w/gFXId0Ybn6pRRAp/cVkwkPtwiII5BEg7pOY02Jpzljy7VddBBQI1AT+WXQp1Ke6SEbausUtsM0wPhXFWdDX55Muc/5VGDFuRDPQYHpHJeyLGDXPwFohdKVxx9qDH1X18RVtos2x4rsDLDQuLUuazRsycLe8xc5p7HfmyIn2ByoNzCuQvcyd7zJ7BRfiiVEI8oJTGTpevl+DSO+CuJYDigINUHJV0aU2GaHIOLKh9KSYe5VKOHVp70gcB9ayIuBO3eKlkIB8p4unqxEKqf1ub2Rv/mN2IYfD0muYQ51fnFo6Td7TjIPPccaYqVaccsTayOzuhneFV9F0X/wiQ8pz5c0VjjIyjnoohvLYsVAmSW9m1ukWirbgexAQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022571.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7563 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Check for both the MMIO and SDMA pathes. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 779f9b0974d2e..8a975eddd75c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -724,6 +724,13 @@ void amdgpu_gmc_flush_gpu_tlb_gart(struct amdgpu_device *adev, struct amdgpu_job *job; int r; + /* + * A GPU reset should flush all TLBs anyway, so no need to do + * this while one is ongoing. + */ + if (!down_read_trylock(&adev->reset_domain->sem)) + return; + ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]); switch (adev->gmc.gart_inv_method) { @@ -738,13 +745,6 @@ void amdgpu_gmc_flush_gpu_tlb_gart(struct amdgpu_device *adev, if (!adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready || !ring->sched.ready || use_mmio) { - /* - * A GPU reset should flush all TLBs anyway, so no need to do - * this while one is ongoing. - */ - if (!down_read_trylock(&adev->reset_domain->sem)) - return; - if (adev->gmc.flush_tlb_needs_extra_type_2) adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, vmhub, 2); @@ -778,11 +778,13 @@ void amdgpu_gmc_flush_gpu_tlb_gart(struct amdgpu_device *adev, dma_fence_wait(fence, false); dma_fence_put(fence); + up_read(&adev->reset_domain->sem); return; error_alloc: mutex_unlock(&adev->mman.default_entity.lock); + up_read(&adev->reset_domain->sem); dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r); } -- 2.55.0