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Tue, 1 Sep 2026 15:10:49 -0500 From: Alex Deucher To: , CC: Alex Deucher Subject: [PATCH 05/31] drm/amdgpu/gmc9: set vmhub funcs for gfxhub and mmhub Date: Tue, 1 Sep 2026 16:10:08 -0400 Message-ID: <20260901201034.2960437-6-alexander.deucher@amd.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260901201034.2960437-1-alexander.deucher@amd.com> References: <20260901201034.2960437-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD1:EE_|IA1PR12MB6385:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ceb01f8-f97a-4e12-473d-08df08651ef3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|23010399003|376014|82310400026|36860700016|1800799024|10067099003|11063799006|18002099003|22082099003|56012099006; X-Microsoft-Antispam-Message-Info: 4hZ8ARzxXkoOHnYIc4Olalw1M7ncN3qRmnmSBEjQgXXI25rdd4rTXeoTl24h72bGmO3HWm2hbbP1l5QxMBTHEAYSX++MSs14cnHystBQLTRiRrS1IZ4R7Ch34xaTvtQIRhNw3Vuoo9Sge6sI5bRWiGHyxwhMCy7aghMq1F1rG/wdGSQxrKRHFLAhs7Kif9Od+aTbrWT5qV/N8onU5DXFxDQCG1H3GDvsKiGIJTnEtbgZ1wYma36KGd53zESC+g0LlNAAyli+OmXgxJ4NE4Wmpm6raobmmmyzECzmXdpj8770dma11JDiYyR+AamfiLoZsPFiJ7XIoeKlLj7gTKY1T2delX+4u6t01IXS3agR6AaU+slPU50qF75OBTtweeoJSLuvXzt0ox3WTllRhme7xr0QlsSH5BDN7I3rVo74PBxi8PyUW1w4yZUudRRyfvg5OzZh6mUah60B8yscQZcKUghg/8Q932+bGKPPdDHSH374GlhBRILQ809gryO8184TRAvWwPUuCsPF38L68J25eU7tO3BBPwr7WRfCmAy9F4gWUjNPt7CR68Pf6XJmalfXauLoD9jl7PkDT8kG5b31aLQsOOS5FkRnF/HgkZ7sCTq3kd2vCw108Z4KnCYzdlEtPGdy11eD2qNFvId0aalC1HY9sUBF5StXn41NF5bG/cSYL2jwV1LsvpPy/8+H0miIRjzMbt72PgSzWbn+boewxw== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6385 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" This was handled in gmc_v9_0 directly. Set the pointers so that we can use rely on the callbacks in the generic gmc helpers. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 33 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 33 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 21 +-------------- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 33 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 32 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 32 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 32 +++++++++++++++++++++++ 7 files changed, 196 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index bfe247b1a333c..f4e6c8b6c2cf9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -410,6 +410,37 @@ static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); } +static void +gfxhub_v1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + /* this is handled in gmc_v9_0.c already */ +} + +static uint32_t gfxhub_v1_0_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static const struct amdgpu_vmhub_funcs gfxhub_v1_0_vmhub_funcs = { + .print_l2_protection_fault_status = gfxhub_v1_0_print_l2_protection_fault_status, + .get_invalidate_req = gfxhub_v1_0_get_invalidate_req, +}; + static void gfxhub_v1_0_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; @@ -439,6 +470,8 @@ static void gfxhub_v1_0_init(struct amdgpu_device *adev) hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ; hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + + hub->vmhub_funcs = &gfxhub_v1_0_vmhub_funcs; } const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c index fbdf46070b38b..fd216e1670abe 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c @@ -539,6 +539,37 @@ static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev, gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, xcc_mask); } +static void +gfxhub_v1_2_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + /* this is handled in gmc_v9_0.c already */ +} + +static uint32_t gfxhub_v1_2_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static const struct amdgpu_vmhub_funcs gfxhub_v1_2_vmhub_funcs = { + .print_l2_protection_fault_status = gfxhub_v1_2_print_l2_protection_fault_status, + .get_invalidate_req = gfxhub_v1_2_get_invalidate_req, +}; + static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask) { struct amdgpu_vmhub *hub; @@ -577,6 +608,8 @@ static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask) hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + + hub->vmhub_funcs = &gfxhub_v1_2_vmhub_funcs; } } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 80f1cf1f21736..73b96efd45484 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -705,25 +705,6 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) } } -static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, - uint32_t flush_type) -{ - u32 req = 0; - - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, - PER_VMID_INVALIDATE_REQ, 1 << vmid); - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); - req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, - CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); - - return req; -} - /** * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore * @@ -785,7 +766,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); hub = &adev->vmhub[vmhub]; - inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); + inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; req = hub->vm_inv_eng0_req + hub->eng_distance * eng; ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 243eabda06077..46b0fc94007cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -464,6 +464,37 @@ static void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); } +static uint32_t mmhub_v1_0_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static void +mmhub_v1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + /* this is handled in gmc_v9_0.c already */ +} + +static const struct amdgpu_vmhub_funcs mmhub_v1_0_vmhub_funcs = { + .print_l2_protection_fault_status = mmhub_v1_0_print_l2_protection_fault_status, + .get_invalidate_req = mmhub_v1_0_get_invalidate_req, +}; + static void mmhub_v1_0_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; @@ -493,6 +524,8 @@ static void mmhub_v1_0_init(struct amdgpu_device *adev) hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ; hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + + hub->vmhub_funcs = &mmhub_v1_0_vmhub_funcs; } static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c index 2adee2b94c37d..84d1dc32728bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c @@ -448,6 +448,37 @@ static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp); } +static void +mmhub_v1_7_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + /* this is handled in gmc_v9_0.c already */ +} + +static uint32_t mmhub_v1_7_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static const struct amdgpu_vmhub_funcs mmhub_v1_7_vmhub_funcs = { + .print_l2_protection_fault_status = mmhub_v1_7_print_l2_protection_fault_status, + .get_invalidate_req = mmhub_v1_7_get_invalidate_req, +}; + static void mmhub_v1_7_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; @@ -476,6 +507,7 @@ static void mmhub_v1_7_init(struct amdgpu_device *adev) hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + hub->vmhub_funcs = &mmhub_v1_7_vmhub_funcs; } static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c index 47d07cd25fc41..4c9f41905b650 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c @@ -577,6 +577,37 @@ static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool } } +static void +mmhub_v1_8_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + /* this is handled in gmc_v9_0.c already */ +} + +static uint32_t mmhub_v1_8_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static const struct amdgpu_vmhub_funcs mmhub_v1_8_vmhub_funcs = { + .print_l2_protection_fault_status = mmhub_v1_8_print_l2_protection_fault_status, + .get_invalidate_req = mmhub_v1_8_get_invalidate_req, +}; + static void mmhub_v1_8_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub; @@ -610,6 +641,7 @@ static void mmhub_v1_8_init(struct amdgpu_device *adev) regVM_INVALIDATE_ENG0_REQ; hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + hub->vmhub_funcs = &mmhub_v1_8_vmhub_funcs; } } diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c index fe0710b55c3ac..af7958931b152 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c @@ -536,6 +536,37 @@ static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool } } +static void +mmhub_v9_4_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + /* this is handled in gmc_v9_0.c already */ +} + +static uint32_t mmhub_v9_4_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, VML2VC0_VM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static const struct amdgpu_vmhub_funcs mmhub_v9_4_vmhub_funcs = { + .print_l2_protection_fault_status = mmhub_v9_4_print_l2_protection_fault_status, + .get_invalidate_req = mmhub_v9_4_get_invalidate_req, +}; + static void mmhub_v9_4_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] = { @@ -584,6 +615,7 @@ static void mmhub_v9_4_init(struct amdgpu_device *adev) mmVML2VC0_VM_INVALIDATE_ENG0_REQ; hub[i]->eng_addr_distance = mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + hub[i]->vmhub_funcs = &mmhub_v9_4_vmhub_funcs; } } -- 2.55.0