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envelope-from=pierrick.bouvier@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Pierrick Bouvier From: Pierrick Bouvier via qemu development Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Pierrick Bouvier --- hw/riscv/k230.c | 1 - hw/riscv/microchip_pfsoc.c | 1 - hw/riscv/opentitan.c | 1 - hw/riscv/shakti_c.c | 1 - hw/riscv/sifive_e.c | 1 - hw/riscv/sifive_u.c | 1 - hw/riscv/spike.c | 1 - hw/riscv/tt_atlantis.c | 1 - hw/riscv/xiangshan_kmh.c | 1 - include/hw/riscv/machines-qom.h | 15 +++------------ target/riscv/machine.c | 12 ------------ 11 files changed, 3 insertions(+), 33 deletions(-) diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 558f30b97e9..72d50d369a9 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -556,7 +556,6 @@ static const TypeInfo k230_machine_typeinfo = { .class_init = k230_machine_class_init, .instance_init = k230_machine_instance_init, .instance_size = sizeof(K230MachineState), - .interfaces = riscv64_machine_interfaces, }; static void k230_machine_init_register_types(void) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4017129c830..42d4fc39734 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -756,7 +756,6 @@ static const TypeInfo microchip_icicle_kit_machine_typeinfo = { .class_init = microchip_icicle_kit_machine_class_init, .instance_init = microchip_icicle_kit_machine_instance_init, .instance_size = sizeof(MicrochipIcicleKitState), - .interfaces = riscv64_machine_interfaces, }; static void microchip_icicle_kit_machine_init_register_types(void) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 5b2f33d5aca..c58d8993303 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -338,7 +338,6 @@ static const TypeInfo open_titan_types[] = { .parent = TYPE_MACHINE, .instance_size = sizeof(OpenTitanState), .class_init = opentitan_machine_class_init, - .interfaces = riscv32_machine_interfaces, } }; diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 835b1f879b7..9fd7856dc24 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -98,7 +98,6 @@ static const TypeInfo shakti_c_machine_type_info = { .class_init = shakti_c_machine_class_init, .instance_init = shakti_c_machine_instance_init, .instance_size = sizeof(ShaktiCMachineState), - .interfaces = riscv64_machine_interfaces, }; static void shakti_c_machine_type_info_register(void) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 71925583bd9..ede7cb52f00 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -168,7 +168,6 @@ static const TypeInfo sifive_e_machine_typeinfo = { .class_init = sifive_e_machine_class_init, .instance_init = sifive_e_machine_instance_init, .instance_size = sizeof(SiFiveEState), - .interfaces = riscv32_64_machine_interfaces, }; static void sifive_e_machine_init_register_types(void) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 57a57c96e16..08687cfc363 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -680,7 +680,6 @@ static const TypeInfo sifive_u_machine_typeinfo = { .class_init = sifive_u_machine_class_init, .instance_init = sifive_u_machine_instance_init, .instance_size = sizeof(SiFiveUState), - .interfaces = riscv32_64_machine_interfaces, }; static void sifive_u_machine_init_register_types(void) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 630b65f5697..3786de4b0b7 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -292,7 +292,6 @@ static const TypeInfo spike_machine_typeinfo = { .class_init = spike_machine_class_init, .instance_init = spike_machine_instance_init, .instance_size = sizeof(SpikeState), - .interfaces = riscv32_64_machine_interfaces, }; static void spike_machine_init_register_types(void) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index d808bcc11c3..5e155726abf 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -609,7 +609,6 @@ static const TypeInfo tt_atlantis_types[] = { .parent = TYPE_MACHINE, .class_init = tt_atlantis_machine_class_init, .instance_size = sizeof(TTAtlantisState), - .interfaces = riscv64_machine_interfaces, }, }; diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 384624d69ad..e02624b62b4 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -216,7 +216,6 @@ static const TypeInfo xiangshan_kmh_machine_info = { .parent = TYPE_MACHINE, .instance_size = sizeof(XiangshanKmhState), .class_init = xiangshan_kmh_machine_class_init, - .interfaces = riscv64_machine_interfaces, }; static void xiangshan_kmh_machine_register_types(void) diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h index 6c0bbdfc159..e5f45b32e69 100644 --- a/include/hw/riscv/machines-qom.h +++ b/include/hw/riscv/machines-qom.h @@ -11,15 +11,6 @@ #include "hw/core/boards.h" -/* - * Interfaces specifying whether a given QOM object is available in - * qemu-system-riscv32, qemu-system-riscv64, or both. - */ - -extern const InterfaceInfo riscv32_machine_interfaces[]; -extern const InterfaceInfo riscv64_machine_interfaces[]; -extern const InterfaceInfo riscv32_64_machine_interfaces[]; - /* * Helper macros for defining machines available in qemu-system-riscv32, * qemu-system-riscv64, or both. @@ -27,14 +18,14 @@ extern const InterfaceInfo riscv32_64_machine_interfaces[]; #define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ - riscv32_machine_interfaces) + NULL) #define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ - riscv64_machine_interfaces) + NULL) #define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \ DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \ - riscv32_64_machine_interfaces) + NULL) #endif diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 59676c94470..22a918cec95 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -580,15 +580,3 @@ const VMStateDescription vmstate_riscv_cpu = { NULL } }; - -const InterfaceInfo riscv32_machine_interfaces[] = { - { } -}; - -const InterfaceInfo riscv64_machine_interfaces[] = { - { } -}; - -const InterfaceInfo riscv32_64_machine_interfaces[] = { - { } -}; -- 2.43.0