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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00018547.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6522 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Charlene Liu [Why & How] streamclk gating sequence update: disable streamclk gating when using streamclk Reviewed-by: Leo Chen Signed-off-by: Charlene Liu Signed-off-by: Ray Wu --- .../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 1 + .../gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c | 14 +++++++++++++- .../gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h | 2 +- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 71903a6c63a0..4fbd40b518cd 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1661,6 +1661,7 @@ void dccg35_set_hdmistreamclk( { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + dccg35_set_hdmistreamclk_rcg(dccg, 0, false); /* set the dtbclk_p source */ dccg35_set_dtbclk_p_src(dccg, src, otg_inst); diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c index 3b03b152da22..c9ea3b166876 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -308,13 +308,25 @@ static void dccg42_init(struct dccg *dccg) } } } +void dccg42_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.hdmistream && !enable) { + DC_LOG_DEBUG("%s: HDMISTREAMCLK0_ROOT_GATE DISABLE = 0 bypassed", __func__); + return; + } + REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, enable ? 1 : 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, enable ? 1 : 0); + DC_LOG_DEBUG("%s: HDMISTREAMCLK0_ROOT_GATE_DISABLE = %d\n", __func__, enable ? 1 : 0); +} static const struct dccg_funcs dccg42_funcs = { .enable_hdmicharclk = dccg401_enable_hdmicharclk, .disable_hdmicharclk = dccg42_disable_hdmicharclk, .set_hdmistreamclk = dccg35_set_hdmistreamclk, - .set_hdmistreamclk_root_clock_gating = dccg35_set_hdmistreamclk_root_clock_gating, + .set_hdmistreamclk_root_clock_gating = dccg42_set_hdmistreamclk_root_clock_gating, .update_dpp_dto = dccg35_update_dpp_dto, .dpp_root_clock_control = dccg35_dpp_root_clock_control, .get_dccg_ref_freq = dccg401_get_dccg_ref_freq, diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h index ebd3cec1a977..198dc7a6c71e 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h @@ -262,7 +262,7 @@ void dccg42_set_pixel_rate_div( enum pixel_rate_div unused); void dccg42_trigger_dio_fifo_resync(struct dccg *dccg); - +void dccg42_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable); struct dccg *dccg42_create( struct dc_context *ctx, const struct dccg_registers *regs, -- 2.43.0