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Wed, 2 Sep 2026 00:06:37 -0500 From: Ray Wu To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Ovidiu Bunea , Michael Strauss , Ray Wu Subject: [PATCH 16/40] drm/amd/display: Set mpc_tree_params->opp_id during OPP resource construct Date: Wed, 2 Sep 2026 12:58:38 +0800 Message-ID: <20260902050411.3473916-17-ray.wu@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260902050411.3473916-1-ray.wu@amd.com> References: <20260902050411.3473916-1-ray.wu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PEPF00000066:EE_|DM4PR12MB7672:EE_ X-MS-Office365-Filtering-Correlation-Id: 4a84fee3-21da-4f44-3d28-08df08affd70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700016|23010399003|376014|6133799003|22082099003|18002099003|56012099006|11063799006|10067099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fHdKqzSntR7paRqOpyfFyZITW7SZdKi3FWq9Ohx6QPKqmUAFs2g6Op0fS2knTJwNuDTVDubqRKahuNbUGQ4TPyrLntqrakbNg0P7QFD1LoJllRuzaHV/jcMyeVVF6KVj5FzT7rizf4Ll4DiyFTyFzCHJFTTTGLDxJImoCXv67qtL1BmpklAG58sV6dpsVifQtw4pG5gW3nTULXork4sKrOY54zxrgSyUTvbS8FZu0qiqTZPa4+toNMYtfIUzDayoFaBpNr36SULfx3rQIx5lS3NgMyoz0UrT1nWC5xJEjfZBaF17r0rwu+I3rTxErIKuOMUopw4qClC9uXCQj7hnUG3U8N6yP3mxj3oL/90RsLcVXqM+VBqOlMpPnMZHeuAaSsq128RsE7rcK6hsOWLfzRC0K+b80yzud29y0AzDL403Vnkq8qr3voF0JK/v5Guy X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 05:06:47.3792 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4a84fee3-21da-4f44-3d28-08df08affd70 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: LV8PEPF00000066.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7672 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Ovidiu Bunea [Why & How] Currently, init_pipes() is the only interface responsible for initializing the OPP->MPCC resource for all pipes. However, during seamless boot transitions, init_pipes() is skipped and we transition directly to an ODM2:1 config where we end up programming the default SW struct state of mpc_tree_params, which is 0. This results in a config where both HUBP0 & HUBP1 are being fed into the same OPP inst, 0 in this case. This is purely a case of programming incorrect SW state initialization values into HW, so fix this by initializing mpc_tree_params with the correct instances during resource construct. Reviewed-by: Michael Strauss Signed-off-by: Ovidiu Bunea Signed-off-by: Ray Wu --- drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c index 881b8da656b2..8486175a3b56 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c @@ -455,6 +455,8 @@ void dcn20_opp_construct(struct dcn20_opp *oppn20, oppn20->base.ctx = ctx; oppn20->base.inst = inst; oppn20->base.funcs = &dcn20_opp_funcs; + oppn20->base.mpc_tree_params.opp_id = inst; + oppn20->base.mpc_tree_params.opp_list = NULL; oppn20->regs = regs; oppn20->opp_shift = opp_shift; -- 2.43.0