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Wed, 2 Sep 2026 00:06:47 -0500 From: Ray Wu To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Alvin Lee , Wenjing Liu , Ray Wu Subject: [PATCH 17/40] drm/amd/display: Add override capability for UTM table params Date: Wed, 2 Sep 2026 12:58:39 +0800 Message-ID: <20260902050411.3473916-18-ray.wu@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260902050411.3473916-1-ray.wu@amd.com> References: <20260902050411.3473916-1-ray.wu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000D:EE_|LV3PR12MB9142:EE_ X-MS-Office365-Filtering-Correlation-Id: 46a7ff3c-b996-408f-2cf9-08df08b002ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|376014|23010399003|1800799024|82310400026|11063799006|3023799007|10067099003|56012099006|22082099003|18092099006|18002099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BrZ+wFQamd/NG6hOpw7/OUxQJOAI4s7X5PZX9LNFF7+nNIxtNI44M9i4eST1bA/ckaS4fHBWUaeFBqNYiR9IcaCdoeIhDI7w7mYCwXLvjEOODdmVZdPoEnmT5FWv+dItBeztkiQh9yDhAkvmLvqz66xQEA/Tyt7kgae7sOy9YzP0nzR8Cookz9AW/WMRlbJClWNThPGnCa8JK5tZ8Cq4UC11/DHWPxR3psSb/vNMGp4umWnlZpgR84WLzzHClMxwP8ZN4sjkLcIvL0JhUXgh3hJawgU8At3cZ6R2BxUJ15s8WEnfViuK1iAteMChe2sNQdzVc8cdEaARLf0NvnV1m/VfZFURTaR3v5vWgPpPN8hkPkEFnlZROygG2ShqBcFzl848dKaqBJxNCNgXph9JqEF1986bDOyXYXQdopf25TQ3cv85hCkldSEjQlyO6sUU X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 05:06:56.3829 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46a7ff3c-b996-408f-2cf9-08df08b002ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9142 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alvin Lee [Why & How] Add calls for overriding UTM table params from PMFW. This is for debug and test purposes only when PMFW has not yet populated the table values correctly. Reviewed-by: Wenjing Liu Signed-off-by: Alvin Lee Signed-off-by: Ray Wu --- .../drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h | 2 +- .../display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 70 +++++++++++++++++-- .../dc/clk_mgr/dcn60/dcn60_smu_driver_if.h | 44 ++++++------ 3 files changed, 88 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h index 6954a54dad89..9b109959bd7f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dalsmc.h @@ -112,7 +112,7 @@ typedef struct { * TABLE_DAL_INIT - Full TABLE_DAL_INIT payload transferred from SMU to DRAM. */ #define TABLE_DAL_INIT 0xD -#define MAX_PPCLK_COUNT 20 +#define MAX_PPCLK_COUNT 22 #define DPM_CLOCK_OFFSET(Ppclk) \ (sizeof(DalInitHeader_t) + (Ppclk) * sizeof(DpmClock_t)) #define UTM_TABLE_OFFSET \ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c index 83989b4b1fdd..2b7740b82161 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c @@ -479,6 +479,39 @@ static int dcn60_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base) return dtb_ref_clk_khz; } +/** + * dcn60_override_dc_mode_limit - Override DC mode limits from the clock table. + * @dc_limit: output DC mode limit to populate + * @clk_table: clock table already populated (and possibly overridden) + * + * Sets the DC mode max frequency for each clock to the highest populated DPM + * level in the clock table. Deriving the limit from the clock table (rather + * than the raw DAL init table) ensures any overrides applied to the clock + * levels are respected. + */ +static void dcn60_override_dc_mode_limit( + struct clk_limit_table_entry *dc_limit, + const struct clk_limit_table *clk_table) +{ + const struct clk_limit_table_entry *entries = clk_table->entries; + const struct clk_limit_num_entries *num_entries = &clk_table->num_entries_per_clk; + + dc_limit->dcfclk_mhz = num_entries->num_dcfclk_levels ? + entries[num_entries->num_dcfclk_levels - 1].dcfclk_mhz : 0; + dc_limit->socclk_mhz = num_entries->num_socclk_levels ? + entries[num_entries->num_socclk_levels - 1].socclk_mhz : 0; + dc_limit->dtbclk_mhz = num_entries->num_dtbclk_levels ? + entries[num_entries->num_dtbclk_levels - 1].dtbclk_mhz : 0; + dc_limit->dispclk_mhz = num_entries->num_dispclk_levels ? + entries[num_entries->num_dispclk_levels - 1].dispclk_mhz : 0; + dc_limit->dppclk_mhz = num_entries->num_dppclk_levels ? + entries[num_entries->num_dppclk_levels - 1].dppclk_mhz : 0; + dc_limit->memclk_mhz = num_entries->num_memclk_levels ? + entries[num_entries->num_memclk_levels - 1].memclk_mhz : 0; + dc_limit->fclk_mhz = num_entries->num_fclk_levels ? + entries[num_entries->num_fclk_levels - 1].fclk_mhz : 0; +} + static unsigned int dcn60_get_dc_mode_limit_mhz(const DpmClock_t *dpm_clk) { if (dpm_clk->NumClocks @@ -495,8 +528,10 @@ static unsigned int dcn60_get_dc_mode_limit_mhz(const DpmClock_t *dpm_clk) * * Sets the DC mode max frequency for each clock. If DcMaxClock equals the * highest DPM level, the limit is set to 0 (no DC-specific cap). + * + * Temporarily unused. */ -static void dcn60_populate_dc_mode_limit( +static void __maybe_unused dcn60_populate_dc_mode_limit( struct clk_limit_table_entry *dc_limit, const DalInitTable_t *init_table) { @@ -578,6 +613,20 @@ static void dcn60_populate_clk_table(struct clk_mgr_internal *clk_mgr, clk_table->num_entries = 1; } +/** + * dcn60_override_clk_table - Override the clock table with hardcoded values. + * @clk_table: clock table to override + * + * Temporary debug/bring-up override that replaces the DPM clock levels + * populated from the DAL init table (see dcn60_populate_clk_table) with a + * fixed set of hardcoded values. Implement any override as needed. + */ +static void dcn60_override_clk_table(struct clk_limit_table *clk_table) +{ + /* Override as needed */ + (void)clk_table; +} + static void dcn60_override_bw_params(struct clk_mgr_internal *clk_mgr, struct clk_bw_params *bw_params) { @@ -605,12 +654,17 @@ static void dcn60_override_bw_params(struct clk_mgr_internal *clk_mgr, bw_params->dc_mode_softmax_memclk = bw_params->dc_mode_limit.memclk_mhz; - /* The qos model stores dchub_v3 as a const view of a mutable table, so - * cast away const to apply the override. - */ - if (bw_params->utm_qos_model && bw_params->utm_qos_model->dchub_v3) + /* Override as needed - temporary for debug only. */ + if (bw_params->utm_qos_model && bw_params->utm_qos_model->dchub_v3) { + dcn6_test_initialize_utm_qos_model_v3( + (struct utm_qos_model *)bw_params->utm_qos_model, + (struct utm_qos_model_dchub_v3 *)bw_params->utm_qos_model->dchub_v3); + + // Override for lsdma here is redundant with the above call, but this may need to outlive + // the test_initialize call for debug purposes so keep it here for now. dcn6_test_override_lsdma_bandwidth_v3( (struct utm_qos_model_dchub_v3 *)bw_params->utm_qos_model->dchub_v3); + } } /** @@ -685,7 +739,9 @@ static bool dcn60_fetch_dal_init_table(struct clk_mgr_internal *clk_mgr) clk_mgr->smu_ver = init_table->Header.SmuVersion; dcn60_populate_clk_table(clk_mgr, &bw_params->clk_table, init_table); - dcn60_populate_dc_mode_limit(&bw_params->dc_mode_limit, init_table); + // Comment out for now - DC mode limit is not yet used in DCN6 and the current + // population from init table will cause undefined behaviors. + //dcn60_populate_dc_mode_limit(&bw_params->dc_mode_limit, init_table); bw_params->num_channels = init_table->MemoryConfig.NumUmcChannels; bw_params->dram_channel_width_bytes = @@ -694,6 +750,8 @@ static bool dcn60_fetch_dal_init_table(struct clk_mgr_internal *clk_mgr) dcn60_populate_utm_qos_model(clk_mgr, &bw_params->utm_qos_model, init_table); dcn60_override_bw_params(clk_mgr, bw_params); + dcn60_override_clk_table(&bw_params->clk_table); + dcn60_override_dc_mode_limit(&bw_params->dc_mode_limit, &bw_params->clk_table); return true; } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_smu_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_smu_driver_if.h index 3e101fa87cfd..ca23518d88b9 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_smu_driver_if.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_smu_driver_if.h @@ -9,27 +9,29 @@ //Only Clks that have DPM descriptors are listed here // This should be the same order as DPM_e typedef enum { - PPCLK_GFXCLK = 0, - PPCLK_BTNCLK = 1, - PPCLK_LCLK = 2, - PPCLK_UCLK = 3, - PPCLK_FCLK = 4, - PPCLK_G7FCLK = 5, - PPCLK_SOCCLK = 6, - PPCLK_ACLK = 7, - PPCLK_DCFCLK = 8, - PPCLK_VPECLK = 9, - PPCLK_DISPCLK = 10, - PPCLK_DPPCLK = 11, - PPCLK_DPREFCLK = 12, - PPCLK_CFPUCLK = 13, - PPCLK_LOGANCLK = 14, - PPCLK_MSPCLK = 15, - PPCLK_MOVADCLK = 16, - PPCLK_DTBCLK = 17, - PPCLK_DCLK_0 = 18, - PPCLK_VCLK_0 = 19, - PPCLK_COUNT = 20, + PPCLK_GFXCLK = 0, + PPCLK_NVECLK1, + PPCLK_NVECLK2, + PPCLK_NVECLK3, + PPCLK_LCLK, + PPCLK_UCLK, + PPCLK_FCLK, + PPCLK_G7FCLK, + PPCLK_SOCCLK, + PPCLK_ACLK, + PPCLK_DCFCLK, + PPCLK_VPECLK, + PPCLK_DISPCLK, + PPCLK_DPPCLK, + PPCLK_DPREFCLK, + PPCLK_CFPUCLK, + PPCLK_LOGANCLK, + PPCLK_MSPHCLK, + PPCLK_MSPLCLK, + PPCLK_MSPEDECLK, + PPCLK_MOVADCLK, + PPCLK_DTBCLK, + PPCLK_COUNT, } PPCLK_e; typedef struct { -- 2.43.0