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Wed, 2 Sep 2026 00:08:16 -0500 From: Ray Wu To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Ray Wu Subject: [PATCH 27/40] drm/amd/display: Test DM IRQ handler source guard Date: Wed, 2 Sep 2026 12:58:49 +0800 Message-ID: <20260902050411.3473916-28-ray.wu@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260902050411.3473916-1-ray.wu@amd.com> References: <20260902050411.3473916-1-ray.wu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PEPF00000068:EE_|SA3PR12MB7782:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f6c0a1d-2d1c-4aa3-512c-08df08b0380b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700016|1800799024|23010399003|376014|22082099003|18002099003|56012099006|11063799006|10067099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9fHKovFlZmCLF9XUf5qPYsnaGmFuTK2BIwSio3Sq2wLjLXVFlnRCcCXYymERcHprhE11jyiRsdhhZb2Obtxd4eTyTOLvWbYYrc6t23J5t6TbGyVCsHkoyevk/bMCsZnAile0FK0pTah2h+ywqdKkJzCKH19YYV/qYtArzoaks2j67aTi/hwm8cesufVaFjrFkM5lNVw/xuxgfkbOSfCGmUa5zsrBChPZKTV5/MkDsbq5KLb9jF2yMN6wR6LZepg7WfjFiBaCkzKv91eZk/L9//eK2Yr3Z1bDA6jFFDuJ0en1Dr2gyhKRVXInbStbvF3UPgE6XGmNU8hEf7NsFO/jkQiv0FgUwuikHMQU77+ce0V5gGDmzji1cqLr2+0BQ4BTHEYir5uqUI3HUYsBbCMW8qAAA6ouQbNcoZ1FK+yTzYH5geVvaED76InhR1ea0BM/ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 05:08:25.7000 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f6c0a1d-2d1c-4aa3-512c-08df08b0380b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: LV8PEPF00000068.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7782 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alex Hung [Why & How] Add dm_test_irq_handler_invalid_source to cover the early return in amdgpu_dm_irq_handler() when dc_interrupt_to_irq_source() cannot map the hardware entry. Reuse the existing unmapped irq_service stub and assert that neither the high- nor the low-context handler is dispatched. Reviewed-by: Roman Li Signed-off-by: Alex Hung Signed-off-by: Ray Wu --- .../amdgpu_dm/tests/amdgpu_dm_irq_test.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c index 37851af59ffe..d7d2dd49b1f0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/tests/amdgpu_dm_irq_test.c @@ -4710,6 +4710,50 @@ static void dm_test_irq_handler_dispatches_work(struct kunit *test) amdgpu_dm_irq_fini(adev); } +/** + * dm_test_irq_handler_invalid_source - Test the IRQ handler source guard + * @test: The KUnit test context + * + * When dc_interrupt_to_irq_source() cannot map the hardware entry it returns + * DC_IRQ_SOURCE_INVALID, which must not be used to index the DM handler + * tables. amdgpu_dm_irq_handler() should bail out early without dispatching + * to either the high- or low-context handlers. + */ +static void dm_test_irq_handler_invalid_source(struct kunit *test) +{ + struct dc_interrupt_params int_params = { 0 }; + struct amdgpu_iv_entry entry = { 0 }; + struct amdgpu_device *adev; + int high_count = 0; + int low_count = 0; + + adev = kunit_kzalloc(test, sizeof(*adev), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, adev); + KUNIT_ASSERT_EQ(test, amdgpu_dm_irq_init(adev), 0); + + /* This stub maps every src_id to DC_IRQ_SOURCE_INVALID. */ + adev->dm.dc = dm_test_alloc_dc_with_irq_service(test, &dm_test_irq_service_funcs_unmapped); + + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = DC_IRQ_SOURCE_VBLANK1; + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, + amdgpu_dm_irq_register_interrupt(adev, &int_params, dm_test_irq_handler_count, + &high_count)); + + int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, + amdgpu_dm_irq_register_interrupt(adev, &int_params, dm_test_irq_handler_count, + &low_count)); + + KUNIT_EXPECT_EQ(test, amdgpu_dm_irq_handler(adev, NULL, &entry), 0); + + flush_workqueue(adev->dm.irq_wq); + KUNIT_EXPECT_EQ(test, high_count, 0); + KUNIT_EXPECT_EQ(test, low_count, 0); + + amdgpu_dm_irq_fini(adev); +} + /* Tests for dm_handle_vmin_vmax_update() */ /** @@ -4953,6 +4997,7 @@ static struct kunit_case amdgpu_dm_irq_tests[] = { KUNIT_CASE(dm_test_register_outbox_irq_handlers_with_dmub), /* amdgpu_dm_irq_handler */ KUNIT_CASE(dm_test_irq_handler_dispatches_work), + KUNIT_CASE(dm_test_irq_handler_invalid_source), /* dm_handle_vmin_vmax_update */ KUNIT_CASE(dm_test_handle_vmin_vmax_update), {} -- 2.43.0