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Wed, 2 Sep 2026 00:08:43 -0500 From: Ray Wu To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Austin Zheng , Dillon Varone , Ray Wu Subject: [PATCH 30/40] drm/amd/display: Update Urgent Burst Calculation To Account For Unbounded Requests Date: Wed, 2 Sep 2026 12:58:52 +0800 Message-ID: <20260902050411.3473916-31-ray.wu@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260902050411.3473916-1-ray.wu@amd.com> References: <20260902050411.3473916-1-ray.wu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PEPF00000069:EE_|IA1PR12MB9524:EE_ X-MS-Office365-Filtering-Correlation-Id: db3289aa-e4a9-4b58-25c2-08df08b04813 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|23010399003|376014|1800799024|82310400026|30052699003|11063799006|5023799004|10067099003|56012099006|22082099003|18002099003|3023799007; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MnrcgNEmYETGgjAzASHmnQsmn94bJXwJ9pfn3mMN7PbyQ9eVK2MwE13dkcGeunkxJXNFK8GFs0Pqf375vVdx6ZpZK7UIjMB3pnQciP5jOdHSD9cs0O3YeRI98CisUHh/AdnxL7VWQsh/bZsaWD5Eey++BLVtHN/fMH+qCRMcm7DpsPjyR3uEVQYm4gF/ftRv+K+LPQp217AxPY9qKf0zhCl03pHtq36uo2at0QZ2PsdqWq564xi6w2+ic/G6lxQgoFhtmbqzcutqkqs/2K0Ax7o90UME6g7IMMimFWcCC4HomDady6v4sq+nlFbO2S7efUmOoZAdyRZl36y0EpETG/7FIYT8unktEifteyWt512e2rmv3pi4GXyRC4B/HjZBo9K+FbD5TLdeMcrWoAplXAMuDYfzm5fC6FfkhluhpS4YQQlLHvGGk+bhZ9OiNexF X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Sep 2026 05:08:52.5946 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db3289aa-e4a9-4b58-25c2-08df08b04813 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: LV8PEPF00000069.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9524 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Austin Zheng [Why & How] dcn5_calculate_urgent_burst_factor function is aware of unbounded request mode making the buffer larger Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Ray Wu --- .../amd/display/dc/dml2_0/dml21/inc/dml_top_types.h | 12 ++++++++++++ .../dc/dml2_0/dml21/src/dml2_cga/dml2_cga_dcn6.c | 4 +++- .../dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 4 ++++ .../dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c | 7 ++++++- .../dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.h | 2 ++ .../dml2_core_dcn5_funcs_mode_programming.c | 4 ++++ .../dml2_core/dml2_core_dcn5_funcs_mode_support.c | 4 ++++ .../dml2_core_dcn6_funcs_mode_programming.c | 2 ++ .../dml2_core/dml2_core_dcn6_funcs_mode_support.c | 4 ++++ .../dml21/src/dml2_core/dml2_core_shared_types.h | 1 + .../dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c | 5 +++++ .../dml21/src/inc/dml2_internal_shared_types.h | 2 ++ 12 files changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index c241ecaf4d7a..5e056839aaf7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -380,6 +380,10 @@ struct dml2_mode_support_info { bool temp_read_or_ppt_support; bool qos_bandwidth_support; bool dcfclk_support; + bool alternate_channel_size_support; + bool EnoughUrgentLatencyHidingSupport; + bool DSCSlicesODMModeSupported; + bool HActiveForDSCSupported; }; // dml2_mode_support_info struct dml2_memory_path_latency { @@ -544,6 +548,14 @@ struct dml2_display_cfg_programming { double max_active_fclk_change_latency_supported; unsigned int min_return_latency_in_dcfclk; + struct { + struct { + double sdp_bw_mbps; + double dram_bw_mbps; + double dram_vm_only_bw_mbps; + } sys_active; + } non_urg_bw_available; + struct { struct { double sdp_bw_mbps; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_cga/dml2_cga_dcn6.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_cga/dml2_cga_dcn6.c index 8c3dd030e775..43ee8a0b21b3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_cga/dml2_cga_dcn6.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_cga/dml2_cga_dcn6.c @@ -56,7 +56,9 @@ static double cga_dcn6_adjust_to_dfs_clock_value_mhz(const struct dml2_clock_gra double vco_divider; double adjusted_clock_mhz; - DML_ASSERT_MSG(adjuster->dispclk_dppclk_vco_speed_mhz > 1, "invalid dispclk_dppclk_vco_speed_mhz value!\n"); + if (adjuster->dispclk_dppclk_vco_speed_mhz == 0.0) + return clk_mhz; + if (clk_mhz == 0) /* There are cases when a clock is not needed */ return 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 64417736a4d9..4f5c95648834 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -357,6 +357,8 @@ dml_get_var_func(svp_prefetch_urg_bw_available_sdp, double, mode_lib->mp.urg_ban dml_get_var_func(svp_prefetch_urg_bw_available_dram, double, mode_lib->mp.urg_bandwidth_available[dml2_core_internal_soc_state_svp_prefetch][dml2_core_internal_bw_dram]); dml_get_var_func(svp_prefetch_urg_bw_available_dram_vm_only, double, mode_lib->mp.urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_svp_prefetch]); +dml_get_var_func(sys_active_non_urg_bw_available_sdp, double, mode_lib->mp.non_urg_bandwidth_available[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]); + dml_get_var_func(urgent_latency, double, mode_lib->mp.UrgentLatency); dml_get_var_func(max_urgent_latency_us, double, mode_lib->ms.support.max_urgent_latency_us); dml_get_var_func(max_non_urgent_latency_us, double, mode_lib->ms.support.max_non_urgent_latency_us); @@ -13350,6 +13352,8 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod out->informative.qos.urg_bw_available.svp_prefetch.dram_bw_mbps = dml_get_svp_prefetch_urg_bw_available_dram(mode_lib); out->informative.qos.urg_bw_available.svp_prefetch.dram_vm_only_bw_mbps = dml_get_svp_prefetch_urg_bw_available_dram_vm_only(mode_lib); + out->informative.qos.non_urg_bw_available.sys_active.sdp_bw_mbps = dml_get_sys_active_non_urg_bw_available_sdp(mode_lib); + out->informative.qos.urg_bw_required.sys_active.sdp_bw_mbps = dml_get_sys_active_urg_bw_required_sdp(mode_lib); out->informative.qos.urg_bw_required.sys_active.dram_bw_mbps = dml_get_sys_active_urg_bw_required_dram(mode_lib); out->informative.qos.urg_bw_required.svp_prefetch.sdp_bw_mbps = dml_get_svp_prefetch_urg_bw_required_sdp(mode_lib); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c index 09047661a411..f00a45f87101 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c @@ -1811,6 +1811,9 @@ void dcn5_calculate_urgent_burst_factor( double VRatioC, double BytePerPixelInDETY, double BytePerPixelInDETC, + bool UnboundedRequestEnabled, + unsigned int CompressedBufferSizeInkByte, + unsigned int DETBufferSizeY, unsigned int DETBufferSizeC, // Output @@ -1837,7 +1840,9 @@ void dcn5_calculate_urgent_burst_factor( DML_LOG_VERBOSE("DML::%s: LineTime = %f\n", __func__, LineTime); DML_ASSERT(VRatio > 0); - LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / swath_width_luma_ub; + unsigned int EffectiveBufferY = DETBufferSizeY + (UnboundedRequestEnabled ? CompressedBufferSizeInkByte * 1024 : 0); + + LinesInDETLuma = EffectiveBufferY / BytePerPixelInDETY / swath_width_luma_ub; DETBufferSizeInTimeLuma = math_floor2(LinesInDETLuma, SwathHeightY) * LineTime / VRatio; if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.h index d4869571db9d..7b5268e100ed 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.h @@ -103,6 +103,8 @@ void dcn5_calculate_urgent_burst_factor( double VRatioC, double BytePerPixelInDETY, double BytePerPixelInDETC, + bool UnboundedRequestEnabled, + unsigned int CompressedBufferSizeInkByte, unsigned int DETBufferSizeY, unsigned int DETBufferSizeC, // Output diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_programming.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_programming.c index 297e21e7c68d..d7a48ca44b68 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_programming.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_programming.c @@ -592,6 +592,8 @@ static bool dcn5_mode_programming(struct dml2_core_calcs_mode_programming_ex *in display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio, mode_lib->mp.BytePerPixelInDETY[k], mode_lib->mp.BytePerPixelInDETC[k], + mode_lib->mp.UnboundedRequestEnabled, + mode_lib->mp.CompressedBufferSizeInkByte, mode_lib->mp.DETBufferSizeY[k], mode_lib->mp.DETBufferSizeC[k], @@ -801,6 +803,8 @@ static bool dcn5_mode_programming(struct dml2_core_calcs_mode_programming_ex *in mode_lib->mp.VRatioPrefetchC[k], mode_lib->mp.BytePerPixelInDETY[k], mode_lib->mp.BytePerPixelInDETC[k], + mode_lib->mp.UnboundedRequestEnabled, + mode_lib->mp.CompressedBufferSizeInkByte, mode_lib->mp.DETBufferSizeY[k], mode_lib->mp.DETBufferSizeC[k], /* Output */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_support.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_support.c index fde2e0ad2529..09519f0f2251 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_support.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_funcs_mode_support.c @@ -1547,6 +1547,8 @@ static void dcn5_ms_calculate_det_buffer_time_value_urgent_burst_factor_and_urge plane->composition.scaler_info.plane1.v_ratio, mode_lib->ms.BytePerPixelInDETY[k], mode_lib->ms.BytePerPixelInDETC[k], + mode_lib->ms.UnboundedRequestEnabled, + mode_lib->ms.CompressedBufferSizeInkByte, mode_lib->ms.DETBufferSizeY[k], mode_lib->ms.DETBufferSizeC[k], @@ -2095,6 +2097,8 @@ static void dcn5_ms_calculate_urgent_burst_factor_for_prefetch( mode_lib->ms.VRatioPreC[k], mode_lib->ms.BytePerPixelInDETY[k], mode_lib->ms.BytePerPixelInDETC[k], + mode_lib->ms.UnboundedRequestEnabled, + mode_lib->ms.CompressedBufferSizeInkByte, mode_lib->ms.DETBufferSizeY[k], mode_lib->ms.DETBufferSizeC[k], /* Output */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c index 39f0cd14ca3e..00194c608f8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_programming.c @@ -1110,6 +1110,8 @@ static void dcn6_mp_initialize_from_solution(struct dml2_core_internal_mode_prog outputs->min_available_urgent_bandwidth_MBps = solution->validation_result.mode_support.bandwidth_upper_bound.dcn5.urgent_bandwidth_kbps / 1000.0; **outputs->urg_bandwidth_available = math_min2(solution->sop_constraint.dcn5.min_available_urgent_bandwidth_KBps / 1000.0, outputs->Dcfclk * utm_soc_bb->urgent_sdp_derate_percent / 100.0 * utm_soc_bb->return_bus_width_bytes); + **outputs->non_urg_bandwidth_available = math_min2(solution->sop_constraint.dcn5.min_available_non_urgent_bandwidth_KBps / 1000.0, + outputs->Dcfclk * utm_soc_bb->nominal_sdp_derate_percent / 100.0 * utm_soc_bb->return_bus_width_bytes); outputs->UrgentLatency = solution->sop_constraint.dcn5.latency.dcn5.urgent_ramp; outputs->TripToMemory = math_max2(solution->sop_constraint.dcn5.latency.dcn5.urgent_ramp, diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c index de81815f098a..166022bb3096 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_funcs_mode_support.c @@ -2140,6 +2140,8 @@ static void dcn6_ms_calculate_det_buffer_time_value_urgent_burst_factor_and_urge plane->composition.scaler_info.plane1.v_ratio, inputs->BytePerPixelInDETY[k], inputs->BytePerPixelInDETC[k], + inputs->UnboundedRequestEnabled, + inputs->CompressedBufferSizeInkByte, inputs->DETBufferSizeY[k], inputs->DETBufferSizeC[k], @@ -3030,6 +3032,8 @@ static void dcn6_ms_calculate_urgent_burst_factor_for_prefetch( inputs->VRatioPreC[k], inputs->BytePerPixelInDETY[k], inputs->BytePerPixelInDETC[k], + inputs->UnboundedRequestEnabled, + inputs->CompressedBufferSizeInkByte, inputs->DETBufferSizeY[k], inputs->DETBufferSizeC[k], /* Output */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h index 289ed250f477..9eabee1fc001 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h @@ -1070,6 +1070,7 @@ struct dml2_core_internal_mode_program { double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc. double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. + double non_urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c index 937205f1f086..67722c45c224 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_utm_soc_bb/dml2_utm_soc_bb_dcn6.c @@ -32,6 +32,8 @@ static void dcn6_sop_table_get_sop_constraint_at_index(const struct dml2_sop_tab constraint->dcn5.latency.dcn5.avg_req_latency_non_urg = dchub->latencies[index].avg_req_latency_non_urg_ps / 1000000.0; constraint->dcn5.latency.dcn5.df_response_time_us = dchub->latencies[index].df_response_time_ps / 1000000.0; constraint->dcn5.min_available_urgent_bandwidth_KBps = table->sop_min_available_urgent_bandwidths_KBps[index]; + constraint->dcn5.min_available_non_urgent_bandwidth_KBps = table->sop_min_available_non_urgent_bandwidths_KBps[index]; + constraint->dcn5.min_sop_index = index; } @@ -134,6 +136,9 @@ static void dml2_utm_soc_bb_dcn6_build_sop_table(struct dml2_sop_table *table, table->sop_min_available_urgent_bandwidths_KBps[i] = (uint32_t) math_floor( total_available_bandwidth.urgent_bandwidth_KBps * (utm_soc_bb->qos_model.dchub_v2->min_urgent_utm_budget_percent / 100.0)); + table->sop_min_available_non_urgent_bandwidths_KBps[i] = (uint32_t)math_floor( + total_available_bandwidth.nominal_bandwidth_KBps + * (utm_soc_bb->qos_model.dchub_v2->min_nominal_utm_budget_percent / 100.0)); } DML_ASSERT_MSG(table->model->sop_count > 0, "qos_model must contain at least 1 sop\n"); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h index 4289f7f998ff..077e4480575a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h @@ -87,6 +87,7 @@ struct dml2_sop_constraint { struct dml2_memory_path_latency latency; struct dml2_soc_operating_point clocks; double min_available_urgent_bandwidth_KBps; // minimum guaranteed urgent bandwidth at active + double min_available_non_urgent_bandwidth_KBps; // minimum guaranteed nominal bandwidth at active } dcn5; }; }; @@ -95,6 +96,7 @@ struct dml2_sop_table { bool is_initialized; const struct utm_qos_model *model; uint32_t sop_min_available_urgent_bandwidths_KBps[MAX_UTM_SOP_COUNT]; + uint32_t sop_min_available_non_urgent_bandwidths_KBps[MAX_UTM_SOP_COUNT]; uint32_t sop_optimal_dcfclks_khz[MAX_UTM_SOP_COUNT]; unsigned int (*get_highest_sop_index)(const struct dml2_sop_table *sop_table); void (*get_sop_constraint_at_index)(const struct dml2_sop_table *sop_table, unsigned int index, struct dml2_sop_constraint *constraint); -- 2.43.0