From: Matthew Auld <matthew.auld@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Matthew Brost" <matthew.brost@intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>
Subject: [PATCH v2 3/5] drm/xe/vram: revamp CPU VRAM mapping
Date: Wed, 2 Sep 2026 11:39:35 +0100 [thread overview]
Message-ID: <20260902103931.826063-10-matthew.auld@intel.com> (raw)
In-Reply-To: <20260902103931.826063-7-matthew.auld@intel.com>
Previously, we called devm_ioremap_wc() for the entire PCI LMEM BAR (which
can be significantly larger than usable memory, e.g., mapping 16G for a
10G card), and then simply assigned subsets of this global mapping to each
tile.
By moving the devm_ioremap_wc() call into vram_region_init() and mapping
on a per-tile basis, we restrict the virtual address space to exactly
the usable_size of each tile. The other big win is that the core kernel
will place a guard page at the end of each per-tile mapping to help
catch OOB CPU writes (e.g. into the flat CCS storage) by triggering an
immediate page fault instead of silent memory corruption.
As a consequence the global vram->mapping is now NULL. But that was
unused anyway, with CPU access already correctly routed through the per
tile mapping.
Assisted-by: Gemini:gemini-3.1-pro-preview
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/xe/xe_vram.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 56cff1e44530..04d831b101bd 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -55,9 +55,6 @@ static int determine_lmem_bar_size(struct xe_device *xe, struct xe_vram_region *
/* XXX: Need to change when xe link code is ready */
lmem_bar->dpa_base = 0;
- /* set up a map to the total memory area. */
- lmem_bar->mapping = devm_ioremap_wc(&pdev->dev, lmem_bar->io_start, lmem_bar->io_size);
-
return 0;
}
@@ -196,7 +193,7 @@ static void vram_fini(void *arg)
struct xe_tile *tile;
int id;
- xe->mem.vram->mapping = NULL;
+ xe_assert(xe, !xe->mem.vram->mapping);
for_each_tile(tile, xe, id) {
tile->mem.vram->mapping = NULL;
@@ -257,8 +254,15 @@ static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram,
return -ENODEV;
}
+ if (vram != xe->mem.vram) {
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+ vram->mapping = devm_ioremap_wc(&pdev->dev, vram->io_start, vram->io_size);
+ if (!vram->mapping)
+ return -ENOMEM;
+ }
+
vram->dpa_base = lmem_bar->dpa_base + offset;
- vram->mapping = lmem_bar->mapping + offset;
vram->usable_size = usable_size;
print_vram_region_info(xe, vram);
--
2.55.0
next prev parent reply other threads:[~2026-09-02 10:39 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 10:39 [PATCH v2 0/5] VRAM health check + CCS fix Matthew Auld
2026-09-02 10:39 ` [PATCH v2 1/5] drm/xe/migrate: support 4K PTEs for identity map Matthew Auld
2026-09-02 10:39 ` [PATCH v2 2/5] drm/xe/vram: report FLAT_CCS base misalignment Matthew Auld
2026-09-02 10:39 ` Matthew Auld [this message]
2026-09-02 10:49 ` [PATCH v2 3/5] drm/xe/vram: revamp CPU VRAM mapping sashiko-bot
2026-09-02 10:56 ` Matthew Auld
2026-09-02 10:39 ` [PATCH v2 4/5] drm/xe: add force option for global invalidation Matthew Auld
2026-09-02 10:39 ` [PATCH v2 5/5] drm/xe/vram: add early VRAM health check Matthew Auld
2026-09-02 10:47 ` ✓ CI.KUnit: success for VRAM health check + CCS fix (rev2) Patchwork
2026-09-02 11:35 ` ✗ Xe.CI.BAT: failure " Patchwork
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