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From: Nirmoy Das <nirmoyd@nvidia.com>
To: JC Chen <jc_chen@diodes.com>,
	Ilpo Jarvinen <ilpo.jarvinen@linux.intel.com>
Cc: Nirmoy Das <nirmoyd@nvidia.com>,
	Bjorn Helgaas <helgaas@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH] PCI: Work around Pericom PI7C9X3G606GPC Port 4 BAR erratum
Date: Wed, 2 Sep 2026 12:08:28 -0700	[thread overview]
Message-ID: <20260902190832.1615829-1-nirmoyd@nvidia.com> (raw)
In-Reply-To: <SI6PR02MB8471ACB5D861E670331B2F47F3A82@SI6PR02MB8471.apcprd02.prod.outlook.com>

Hi JC,

On 01.09.26 04:51, JC Chen[陳饒靜] wrote:
> => P4 has BAR0 and MSI-X capability when CDEP function is enabled. If
> the CDEP function is disabled, Port 4 is no BAR0 and no MSI-X
> capability. However, in our design, even CDEP function is disabled, we
> still check whether the memory address "hit" P4's MSI-X tables or not.
[...]

Thanks for the confirmation.

I will send a v2 with a commit log that describes the mechanism and the
affected topology.

Regards,
Nirmoy

      reply	other threads:[~2026-09-02 19:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-23 16:10 [RFC PATCH] PCI: Work around Pericom PI7C9X3G606GPC Port 4 BAR erratum Nirmoy Das
2026-07-23 16:16 ` sashiko-bot
2026-07-23 20:54 ` Bjorn Helgaas
2026-07-24  8:36   ` JC Chen[陳饒靜]
2026-08-26 14:28     ` Ilpo Järvinen
2026-08-27  0:13       ` JC Chen[陳饒靜]
2026-08-27  6:45         ` JC Chen[陳饒靜]
2026-08-31 15:29       ` Nirmoy Das
2026-09-01  2:51         ` JC Chen[陳饒靜]
2026-09-02 19:08           ` Nirmoy Das [this message]

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