From: sashiko-bot@kernel.org
To: "Cristian Ciocaltea" <cristian.ciocaltea@collabora.com>
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org, robh@kernel.org
Subject: Re: [PATCH v4 13/14] drm/rockchip: dw_hdmi_qp: Enable YUV420 output format
Date: Wed, 02 Sep 2026 23:08:09 +0000 [thread overview]
Message-ID: <20260902230809.E47841F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260903-dw-hdmi-qp-yuv-v4-13-fb45bf4147eb@collabora.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Hardware PHY is programmed and driver software state is mutated during the DRM atomic_check phase.
--
commit 37fcce32843c9e542a409c0b36a4aca043a38c1a
Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
drm/rockchip: dw_hdmi_qp: Enable YUV420 output format
Both RK3576 and RK3588 SoCs are capable of driving the YUV420 output
color format, and the required bus-format handling and VOP2 support are
already in place. Advertise it via the platform supported formats so
the HDMI core can select it.
Tested-by: Igor Paunovic <royalnet026@gmail.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
> index 78473f9a0fce3..1af29066a0a31 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
> @@ -611,7 +611,8 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
>
> plat_data.supported_formats = BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444) |
> BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444) |
> - BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422);
> + BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422) |
> + BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420);
[Severity: High]
This is a pre-existing issue, but I noticed a potential problem in how the
atomic state machine is handled.
In dw_hdmi_qp_rockchip_encoder_atomic_check():
ret = phy_configure(hdmi->phy, &phy_cfg);
if (!ret) {
hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate;
s->output_type = DRM_MODE_CONNECTOR_HDMIA;
s->output_bpc = conn_state->hdmi.output_bpc;
s->bus_format = ingest_fmt;
Does this actively program the hardware PHY and mutate global driver state
(hdmi->tmds_char_rate) during the DRM atomic_check phase?
If userspace issues a DRM atomic test-only commit, it appears this will
overwrite hdmi->tmds_char_rate. Later, when the actual atomic commit is
performed with the same configuration, the early-return condition at the
beginning of the function will evaluate to true:
if (hdmi->tmds_char_rate == conn_state->hdmi.tmds_char_rate &&
s->output_bpc == conn_state->hdmi.output_bpc &&
s->bus_format == ingest_fmt)
return 0;
Will this cause the driver to incorrectly skip configuring the PHY during the
actual commit phase?
Also, could calling phy_configure() outside of the enable paths bypass
expected runtime PM references, risking bus faults if the block is suspended?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260903-dw-hdmi-qp-yuv-v4-0-fb45bf4147eb@collabora.com?part=13
next prev parent reply other threads:[~2026-09-02 23:08 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 22:54 [PATCH v4 00/14] Support 10-bit YUV422 and 8/10-bit YUV420 color format on DW HDMI QP Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 01/14] dt-bindings: display: vop2: Add missing reset properties Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 02/14] drm/rockchip: vop2: Fix resource leak on vop2_enable() error path Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 23:03 ` sashiko-bot
2026-09-02 22:54 ` [PATCH v4 03/14] drm/rockchip: vop2: Balance state on atomic_enable() error paths Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 04/14] drm/rockchip: vop2: Send pending event when atomic_enable() fails Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 05/14] drm/rockchip: vop2: Avoid division by zero when computing max_dclk Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 06/14] drm/rockchip: vop2: Fix VOP2_MAX_DCLK_RATE overflow on 32-bit Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 23:01 ` sashiko-bot
2026-09-02 22:54 ` [PATCH v4 07/14] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 08/14] drm/rockchip: vop2: Avoid DCLK source switch for 10-bit YUV422 output Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 09/14] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 23:01 ` sashiko-bot
2026-09-02 22:54 ` [PATCH v4 10/14] drm/rockchip: vop2: Switch to enum vop_csc_format Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 11/14] drm/bridge: dw-hdmi-qp: Log resolution and refresh rate in atomic_enable() Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 22:54 ` [PATCH v4 12/14] drm/rockchip: dw_hdmi_qp: Support 10-bit YUV422 output format Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 23:06 ` sashiko-bot
2026-09-02 22:54 ` [PATCH v4 13/14] drm/rockchip: dw_hdmi_qp: Enable YUV420 " Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
2026-09-02 23:08 ` sashiko-bot [this message]
2026-09-02 22:54 ` [PATCH v4 14/14] arm64: dts: rockchip: Add RK3588 VOP2 resets Cristian Ciocaltea
2026-09-02 22:54 ` Cristian Ciocaltea
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