From: kernel test robot <lkp@intel.com>
To: Bokun Zhang <Bokun.Zhang@amd.com>
Cc: oe-kbuild-all@lists.linux.dev, Alex Deucher <alexander.deucher@amd.com>
Subject: [linux-next:master 1091/3131] drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:830:43: sparse: sparse: invalid assignment: |=
Date: Thu, 03 Sep 2026 03:27:32 +0800 [thread overview]
Message-ID: <202609030309.Brgg9wSf-lkp@intel.com> (raw)
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 32b6ef9a5d0eca44f9cd91f52f4faa89f145a0de
commit: 98ba50b2ef1397635ff03091b396b93d0850d50a [1091/3131] drm/amdgpu: Add VCN v5.0.2 SRIOV code path
config: um-randconfig-r134-20260902 (https://download.01.org/0day-ci/archive/20260903/202609030309.Brgg9wSf-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
sparse: v0.6.5-rc1
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260903/202609030309.Brgg9wSf-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202609030309.Brgg9wSf-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:830:43: sparse: sparse: invalid assignment: |=
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:830:43: sparse: left side has type unsigned int
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:830:43: sparse: right side has type restricted __le32
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:90:35: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned int [usertype] present_flag_0 @@ got restricted __le32 [usertype] @@
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:90:35: sparse: expected unsigned int [usertype] present_flag_0
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:90:35: sparse: got restricted __le32 [usertype]
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:358:16: sparse: sparse: cast to restricted __le32
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c:423:16: sparse: sparse: cast to restricted __le32
vim +830 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
707
708
709 /**
710 * vcn_v5_0_2_start_sriov - VCN start under SRIOV env
711 */
712
713 static int vcn_v5_0_2_start_sriov(struct amdgpu_device *adev)
714 {
715 int i, vcn_inst;
716 struct amdgpu_ring *ring_enc;
717 uint64_t cache_addr;
718 uint64_t rb_enc_addr;
719 uint64_t ctx_addr;
720 uint32_t param, resp, expected;
721 uint32_t offset, cache_size;
722 uint32_t tmp, timeout;
723
724 struct amdgpu_mm_table *table = &adev->virt.mm_table;
725 uint32_t *table_loc;
726 uint32_t table_size;
727 uint32_t size, size_dw;
728 uint32_t init_status;
729
730 struct mmsch_v5_0_cmd_direct_write
731 direct_wt = { {0} };
732 struct mmsch_v5_0_cmd_direct_read_modify_write
733 direct_rd_mod_wt = { {0} };
734 struct mmsch_v5_0_cmd_end end = { {0} };
735 struct mmsch_v5_0_init_header header;
736
737 struct amdgpu_vcn5_fw_shared *fw_shared;
738 struct amdgpu_fw_shared_rb_setup *rb_setup;
739
740 direct_wt.cmd_header.command_type =
741 MMSCH_COMMAND__DIRECT_REG_WRITE;
742 direct_rd_mod_wt.cmd_header.command_type =
743 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
744 end.cmd_header.command_type = MMSCH_COMMAND__END;
745
746 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
747 vcn_inst = GET_INST(VCN, i);
748
749 vcn_v5_0_2_fw_shared_init(adev, vcn_inst);
750
751 memset(&header, 0, sizeof(struct mmsch_v5_0_init_header));
752 header.version = MMSCH_VERSION;
753 header.total_size = sizeof(struct mmsch_v5_0_init_header) >> 2;
754
755 table_loc = (uint32_t *)table->cpu_addr;
756 table_loc += header.total_size;
757
758 table_size = 0;
759
760 MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
761 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
762
763 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4);
764
765 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
766 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
767 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
768 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
769
770 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
771 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
772 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
773
774 offset = 0;
775 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
776 regUVD_VCPU_CACHE_OFFSET0), 0);
777 } else {
778 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
779 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
780 lower_32_bits(adev->vcn.inst[i].gpu_addr));
781 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
782 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
783 upper_32_bits(adev->vcn.inst[i].gpu_addr));
784 offset = cache_size;
785 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
786 regUVD_VCPU_CACHE_OFFSET0),
787 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
788 }
789
790 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
791 regUVD_VCPU_CACHE_SIZE0),
792 cache_size);
793
794 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;
795 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
796 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr));
797 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
798 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
799 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
800 regUVD_VCPU_CACHE_OFFSET1), 0);
801 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
802 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE);
803
804 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +
805 AMDGPU_VCN_STACK_SIZE;
806
807 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
808 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr));
809
810 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
811 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
812
813 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
814 regUVD_VCPU_CACHE_OFFSET2), 0);
815
816 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
817 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE);
818
819 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;
820 rb_setup = &fw_shared->rb_setup;
821
822 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];
823 ring_enc->wptr = 0;
824 rb_enc_addr = ring_enc->gpu_addr;
825
826 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
827 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
828 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
829 rb_setup->rb_size = ring_enc->ring_size / 4;
> 830 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
831
832 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
833 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
834 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
835 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
836 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
837 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
838 MMSCH_V5_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
839 regUVD_VCPU_NONCACHE_SIZE0),
840 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
841 MMSCH_V5_0_INSERT_END();
842
843 header.vcn0.init_status = 0;
844 header.vcn0.table_offset = header.total_size;
845 header.vcn0.table_size = table_size;
846 header.total_size += table_size;
847
848 /* Send init table to mmsch */
849 size = sizeof(struct mmsch_v5_0_init_header);
850 table_loc = (uint32_t *)table->cpu_addr;
851 memcpy((void *)table_loc, &header, size);
852
853 ctx_addr = table->gpu_addr;
854 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
855 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
856
857 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);
858 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
859 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
860 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp);
861
862 size = header.total_size;
863 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size);
864
865 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0);
866
867 param = 0x00000001;
868 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param);
869 tmp = 0;
870 timeout = amdgpu_emu_mode ? 1000000 : 1000;
871 resp = 0;
872 expected = MMSCH_VF_MAILBOX_RESP__OK;
873 while (resp != expected) {
874 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);
875 if (resp != 0)
876 break;
877
878 udelay(10);
879 tmp = tmp + 10;
880 if (tmp >= timeout) {
881 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
882 " waiting for regMMSCH_VF_MAILBOX_RESP "\
883 "(expected=0x%08x, readback=0x%08x)\n",
884 tmp, expected, resp);
885 return -EBUSY;
886 }
887 }
888
889 init_status = ((struct mmsch_v5_0_init_header *)(table_loc))->vcn0.init_status;
890 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
891 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) {
892 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
893 "status for VCN%x: 0x%x\n", resp, vcn_inst, init_status);
894 }
895 }
896
897 return 0;
898 }
899
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
reply other threads:[~2026-09-02 19:27 UTC|newest]
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