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Wed, 02 Sep 2026 21:46:46 -0700 (PDT) Received: from localhost.localdomain ([76.133.142.170]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1431994db8csm2337726c88.9.2026.09.02.21.46.46 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 21:46:46 -0700 (PDT) From: 54weasels <54weasels@gmail.com> To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, balaton@eik.bme.hu, 54weasels <54weasels@gmail.com> Subject: [PATCH v5 3/6] target/m68k: Fix NMI pending for Level 7 interrupts Date: Wed, 2 Sep 2026 21:45:16 -0700 Message-ID: <20260903044626.24453-4-54weasels@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260903044626.24453-1-54weasels@gmail.com> References: <20260903044626.24453-1-54weasels@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=54weasels@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Why this change is made & How it will be used: Level 7 interrupts are Non-Maskable Interrupts (NMI) on the M68k architecture. The hardware asserts an NMI only on the rising edge of the level 7 signal. The current QEMU implementation treats level 7 like a standard level interrupt. This patch ensures proper NMI edge-triggered semantics for level 7, which is strictly required by the Sun-3 keyboard/mouse NMI routing logic. Impact on existing functionality: Corrects NMI edge-triggering for all M68k boards, adhering closely to the Motorola specifications. Existing boards will now correctly require an edge transition to trigger consecutive NMIs. Signed-off-by: 54weasels <54weasels@gmail.com> --- target/m68k/cpu.h | 4 ++++ target/m68k/helper.c | 6 ++++++ target/m68k/op_helper.c | 14 ++++++-------- 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7cf3791108..8f4dec4a40 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -25,6 +25,9 @@ #include "exec/cpu-interrupt.h" #include "qemu/cpu-float.h" #include "cpu-qom.h" +#include "exec/cpu-defs.h" + +#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_1 #define OS_BYTE 0 #define OS_WORD 1 @@ -148,6 +151,7 @@ typedef struct CPUArchState { int pending_vector; int pending_level; + bool nmi_pending; /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 68f523ea84..93739ccda7 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -949,6 +949,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector) CPUState *cs = CPU(cpu); CPUM68KState *env = &cpu->env; + if (level == 7 && env->pending_level != 7) { + env->nmi_pending = true; + } else if (level != 7) { + env->nmi_pending = false; + } + env->pending_level = level; env->pending_vector = vector; if (level) { diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 38f7a68981..30af4a2631 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -522,14 +522,12 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUM68KState *env = cpu_env(cs); - if (interrupt_request & CPU_INTERRUPT_HARD - && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) { - /* - * Real hardware gets the interrupt vector via an IACK cycle - * at this point. Current emulated hardware doesn't rely on - * this, so we provide/save the vector when the interrupt is - * first signalled. - */ + if (env->nmi_pending) { + env->nmi_pending = false; + cs->exception_index = env->pending_vector; + do_interrupt_m68k_hardirq(env); + return true; + } else if (((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) { cs->exception_index = env->pending_vector; do_interrupt_m68k_hardirq(env); return true; -- 2.50.1 (Apple Git-155)