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Wed, 02 Sep 2026 21:46:49 -0700 (PDT) Received: from localhost.localdomain ([76.133.142.170]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1431994db8csm2337726c88.9.2026.09.02.21.46.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 02 Sep 2026 21:46:48 -0700 (PDT) From: 54weasels <54weasels@gmail.com> To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, balaton@eik.bme.hu, 54weasels <54weasels@gmail.com> Subject: [PATCH v5 4/6] target/m68k: Extract Function Codes during TLB fills Date: Wed, 2 Sep 2026 21:45:17 -0700 Message-ID: <20260903044626.24453-5-54weasels@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260903044626.24453-1-54weasels@gmail.com> References: <20260903044626.24453-1-54weasels@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=54weasels@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Why this change is made & How it will be used: The Motorola 68020 architecture utilizes 3-bit Function Codes (FC0-FC2) to distinguish between User/Supervisor Data and Program memory spaces during MMU translation. Previously, QEMU's TLB fills did not explicitly extract or pass these codes down to the translation hooks. This patch extracts the explicit Function Codes (either natively or via the `moves` instruction) and packs them into the `access_type` field. This is required for the upcoming Sun-3 emulation, whose external MMU hardware maps entirely different physical address spaces depending on the Function Code asserted on the bus. Impact on existing functionality: This change introduces no functional impact to existing ColdFire or Mac/Quadra m68k emulation targets. The extraction logic gracefully defaults to standard mapping modes for platforms that do not implement a custom MMU intercept hook, preserving existing TLB behavior. Signed-off-by: 54weasels <54weasels@gmail.com> --- target/m68k/cpu.c | 4 ++-- target/m68k/cpu.h | 10 ++++++---- target/m68k/helper.c | 26 ++++++++++++++++++++++++++ target/m68k/translate.c | 10 ++++++---- 4 files changed, 40 insertions(+), 10 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 6012dc3186..5d90bb075e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -52,8 +52,8 @@ static TCGTBCPUState m68k_get_tb_cpu_state(CPUState *cs) flags = (env->macsr >> 4) & TB_FLAGS_MACSR; if (env->sr & SR_S) { flags |= TB_FLAGS_MSR_S; - flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; - flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; + flags |= (env->sfc << TB_FLAGS_SFC_S_BIT) & TB_FLAGS_SFC_S; + flags |= (env->dfc << TB_FLAGS_DFC_S_BIT) & TB_FLAGS_DFC_S; } if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { flags |= TB_FLAGS_TRACE; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 8f4dec4a40..aadaea770a 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -604,12 +604,14 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, #define TB_FLAGS_MSR_S_BIT 13 #define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) #define TB_FLAGS_SFC_S_BIT 14 -#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) -#define TB_FLAGS_DFC_S_BIT 15 -#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) -#define TB_FLAGS_TRACE 16 +#define TB_FLAGS_SFC_S (7 << TB_FLAGS_SFC_S_BIT) /* 3 Bits reserved */ +#define TB_FLAGS_DFC_S_BIT 17 +#define TB_FLAGS_DFC_S (7 << TB_FLAGS_DFC_S_BIT) /* 3 Bits reserved */ +#define TB_FLAGS_TRACE 20 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) +#define MMU_MOVES_FC_BASE 2 /* mmu_idx 2-9 correspond to FC 0-7 */ + void dump_mmu(CPUM68KState *env); #endif diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 93739ccda7..f3ee95441a 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -975,6 +975,32 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, int ret; target_ulong page_size; + if (qemu_access_type == MMU_INST_FETCH) { + access_type = ACCESS_CODE; + } else { + access_type = ACCESS_DATA; + if (qemu_access_type == MMU_DATA_STORE) { + access_type |= ACCESS_STORE; + } + } + + /* Decode explicit Function Codes from moves instructions */ + if (mmu_idx >= MMU_MOVES_FC_BASE) { + uint8_t fc = mmu_idx - MMU_MOVES_FC_BASE; + access_type |= (fc << 8); /* Pack explicit FC into access type */ + if (fc != 1 && fc != 2) { + access_type |= ACCESS_SUPER; + } + } else { + /* Standard memory accesses map logically to normal M68K FCs */ + if (mmu_idx == MMU_KERNEL_IDX) { + access_type |= ACCESS_SUPER; + access_type |= ((qemu_access_type == MMU_INST_FETCH ? 6 : 5) << 8); + } else { + access_type |= ((qemu_access_type == MMU_INST_FETCH ? 2 : 1) << 8); + } + } + if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) { /* MMU disabled */ tlb_set_page(cs, address & TARGET_PAGE_MASK, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c89ef213ed..5ca25a4881 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -163,10 +163,12 @@ static void do_writebacks(DisasContext *s) #define IS_USER(s) 1 #else #define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S)) -#define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \ - MMU_KERNEL_IDX : MMU_USER_IDX) -#define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \ - MMU_KERNEL_IDX : MMU_USER_IDX) +#define SFC_INDEX(s) (MMU_MOVES_FC_BASE + \ + (((s)->base.tb->flags & TB_FLAGS_SFC_S) >> \ + TB_FLAGS_SFC_S_BIT)) +#define DFC_INDEX(s) (MMU_MOVES_FC_BASE + \ + (((s)->base.tb->flags & TB_FLAGS_DFC_S) >> \ + TB_FLAGS_DFC_S_BIT)) #endif typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); -- 2.50.1 (Apple Git-155)