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([180.150.112.50]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1431990a39bsm2770619c88.3.2026.09.02.22.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 22:52:56 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , Portia Stephens , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 06/16] hw/riscv/cps: Map interrupt controllers in SoC container Date: Thu, 3 Sep 2026 15:21:20 +0930 Message-ID: <20260903055131.257903-7-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260903055131.257903-1-joel@jms.id.au> References: <20260903055131.257903-1-joel@jms.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=joel.stan@gmail.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org The CPS device maps some devices into a container region, but the ACLINT and APLIC were mapped directly to system_memory. Pass the container memory region to the interrupt controller helpers so all CPS devices live in the container. The location of devices in memory for the boston-aia machine is unchanged. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Joel Stanley --- hw/riscv/cps.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index d2fd9638a08d..21daaf4943d8 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -135,7 +135,7 @@ static void riscv_cps_realize(DeviceState *dev, Error **errp) for (i = 0; i < num_of_clusters; i++) { uint64_t cm_base = GLOBAL_CM_BASE + (CM_SIZE * i); uint32_t hartid_base = i << MHARTID_CLUSTER_SHIFT; - s->aplic = riscv_aplic_create(get_system_memory(), + s->aplic = riscv_aplic_create(&s->container, cm_base + AIA_PLIC_M_OFFSET, AIA_PLIC_M_SIZE, hartid_base, /* hartid_base */ @@ -143,7 +143,7 @@ static void riscv_cps_realize(DeviceState *dev, Error **errp) APLIC_NUM_SOURCES, APLIC_NUM_PRIO_BITS, false, true, NULL); - riscv_aplic_create(get_system_memory(), + riscv_aplic_create(&s->container, cm_base + AIA_PLIC_S_OFFSET, AIA_PLIC_S_SIZE, hartid_base, /* hartid_base */ @@ -153,10 +153,10 @@ static void riscv_cps_realize(DeviceState *dev, Error **errp) false, false, s->aplic); /* PLIC changes msi_nonbroken to ture. We revert the change. */ msi_nonbroken = false; - riscv_aclint_swi_create(get_system_memory(), + riscv_aclint_swi_create(&s->container, cm_base + AIA_CLINT_OFFSET, hartid_base, MAX_HARTS, false); - riscv_aclint_mtimer_create(get_system_memory(), + riscv_aclint_mtimer_create(&s->container, cm_base + AIA_CLINT_OFFSET + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, -- 2.47.3