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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce5936a5esm51782465e9.3.2026.09.03.03.45.29 for (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 03 Sep 2026 03:45:29 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 47/51] hw/riscv: remove machines-qom.h Date: Thu, 3 Sep 2026 12:39:31 +0200 Message-ID: <20260903103936.62355-48-philmd@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260903103936.62355-1-philmd@oss.qualcomm.com> References: <20260903103936.62355-1-philmd@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=YcmNIQRf c=1 sm=1 tr=0 ts=6a994fcc cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 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qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Pierrick Bouvier Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20260901202043.26532-15-pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/riscv/machines-qom.h | 14 -------------- configs/targets/riscv32-softmmu.c | 1 - configs/targets/riscv64-softmmu.c | 1 - hw/core/null-machine.c | 1 - hw/riscv/boston-aia.c | 1 - hw/riscv/k230.c | 1 - hw/riscv/microblaze-v-generic.c | 1 - hw/riscv/microchip_pfsoc.c | 1 - hw/riscv/opentitan.c | 1 - hw/riscv/shakti_c.c | 1 - hw/riscv/sifive_e.c | 1 - hw/riscv/sifive_u.c | 1 - hw/riscv/spike.c | 1 - hw/riscv/tt_atlantis.c | 1 - hw/riscv/virt.c | 1 - hw/riscv/xiangshan_kmh.c | 1 - target-info-qom.c | 1 - target/riscv/machine.c | 1 - 18 files changed, 31 deletions(-) delete mode 100644 include/hw/riscv/machines-qom.h diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h deleted file mode 100644 index 79d212eeb7d..00000000000 --- a/include/hw/riscv/machines-qom.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * QOM type definitions for riscv32 / riscv64 machines - * - * Copyright (c) rev.ng Labs Srl. - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#ifndef HW_RISCV_MACHINES_QOM_H -#define HW_RISCV_MACHINES_QOM_H - -#include "hw/core/boards.h" - -#endif diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c index c1d94679c7e..0829ab84de5 100644 --- a/configs/targets/riscv32-softmmu.c +++ b/configs/targets/riscv32-softmmu.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qemu/target-info-impl.h" #include "qemu/target-info-init.h" -#include "hw/riscv/machines-qom.h" #include "target/riscv/cpu-qom.h" #include "target/riscv/cpu-param.h" diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c index f648a5c8944..553bd1f75fe 100644 --- a/configs/targets/riscv64-softmmu.c +++ b/configs/targets/riscv64-softmmu.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qemu/target-info-impl.h" #include "qemu/target-info-init.h" -#include "hw/riscv/machines-qom.h" #include "target/riscv/cpu-qom.h" #include "target/riscv/cpu-param.h" diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 2f008c4a702..60254913019 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -16,7 +16,6 @@ #include "hw/core/boards.h" #include "system/address-spaces.h" #include "hw/core/cpu.h" -#include "hw/riscv/machines-qom.h" static void machine_none_init(MachineState *mch) { diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c index 30eff10bc5f..b90da096ea8 100644 --- a/hw/riscv/boston-aia.c +++ b/hw/riscv/boston-aia.c @@ -18,7 +18,6 @@ #include "hw/ide/ahci-pci.h" #include "hw/core/loader.h" #include "hw/riscv/cps.h" -#include "hw/riscv/machines-qom.h" #include "hw/pci-host/xilinx-pcie.h" #include "hw/core/qdev-properties.h" #include "qapi/error.h" diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 72d50d369a9..34905bb1702 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -26,7 +26,6 @@ #include "hw/core/sysbus.h" #include "hw/riscv/k230.h" #include "hw/riscv/boot.h" -#include "hw/riscv/machines-qom.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" #include "hw/char/serial-mm.h" diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c index 503e8e08992..b0494b1ac50 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -25,7 +25,6 @@ #include "system/address-spaces.h" #include "hw/char/xilinx_uartlite.h" #include "hw/misc/unimp.h" -#include "hw/riscv/machines-qom.h" #define LMB_BRAM_SIZE (128 * KiB) #define MEMORY_BASEADDR 0x80000000 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 42d4fc39734..60bb96da016 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -49,7 +49,6 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/machines-qom.h" #include "hw/riscv/microchip_pfsoc.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index c58d8993303..8cd660dd415 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -26,7 +26,6 @@ #include "hw/core/boards.h" #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" -#include "hw/riscv/machines-qom.h" #include "qemu/units.h" #include "system/system.h" #include "system/address-spaces.h" diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 9fd7856dc24..a205a213324 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "hw/core/boards.h" #include "hw/riscv/shakti_c.h" -#include "hw/riscv/machines-qom.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/intc/sifive_plic.h" diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index ede7cb52f00..1acfea49668 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -40,7 +40,6 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" -#include "hw/riscv/machines-qom.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/sifive_plic.h" diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 08687cfc363..997ee91aa0e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -51,7 +51,6 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" -#include "hw/riscv/machines-qom.h" #include "hw/riscv/fdt-common.h" #include "hw/char/sifive_uart.h" #include "hw/intc/riscv_aclint.h" diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 3786de4b0b7..e36fe996b09 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -34,7 +34,6 @@ #include "hw/riscv/boot.h" #include "hw/riscv/fdt-common.h" #include "hw/riscv/numa.h" -#include "hw/riscv/machines-qom.h" #include "hw/char/riscv_htif.h" #include "hw/intc/riscv_aclint.h" #include "chardev/char.h" diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 5e155726abf..7d02868b222 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -20,7 +20,6 @@ #include "hw/riscv/boot.h" #include "hw/riscv/fdt-common.h" -#include "hw/riscv/machines-qom.h" #include "hw/riscv/riscv_hart.h" #include "hw/char/serial-mm.h" diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d2ae321a376..dd396410178 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -36,7 +36,6 @@ #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/fdt-common.h" -#include "hw/riscv/machines-qom.h" #include "hw/riscv/numa.h" #include "kvm/kvm_riscv.h" #include "hw/firmware/smbios.h" diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index e02624b62b4..247a0b5d1f2 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -41,7 +41,6 @@ #include "hw/riscv/boot.h" #include "hw/riscv/xiangshan_kmh.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/machines-qom.h" #include "system/system.h" static const MemMapEntry xiangshan_kmh_memmap[] = { diff --git a/target-info-qom.c b/target-info-qom.c index f98d3d7698e..6965e4d1169 100644 --- a/target-info-qom.c +++ b/target-info-qom.c @@ -12,7 +12,6 @@ #include "qemu/target-info-impl.h" #include "qemu/target-info-init.h" #include "qemu/target-info-qom.h" -#include "hw/riscv/machines-qom.h" static void target_info_qom_class_init(ObjectClass *oc, const void * data) { diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 22a918cec95..c3f5a255099 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -24,7 +24,6 @@ #include "migration/cpu.h" #include "exec/icount.h" #include "target/riscv/tcg/debug.h" -#include "hw/riscv/machines-qom.h" #ifdef CONFIG_KVM #include "kvm/kvm_riscv.h" #endif -- 2.53.0