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envelope-from=bin.meng@processmission.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The Phytium E2000Q is a heterogeneous Armv8 SoC with two FTC664 cores and two FTC310 cores. This series adds CPU definitions and a shared SoC model, then uses it for two machines: - phytium-pi, with firmware and Linux on SD0 - phytium-e2000-come, with firmware in QSPI NOR and Linux on an AHCI1 SATA disk The machines support the vendor firmware path from the on-chip Phytium Boot ROM (PBR) handoff through Processor Base Firmware (PBF), TF-A, OP-TEE, U-Boot, and Linux. They can also directly boot SDK Linux kernels when supplied with matching board device trees. The PBR model does not execute undocumented ROM code. It parses the selected fip-all.bin, validates the PBF, TF-A FIP, and platform parameter records, and reconstructs the observed handoff state. The MHU model handles the private SCMI power-domain requests needed to release secondary CPUs and exposes a separate Base-protocol channel to Linux. The shared E2000Q machine provides GICv3/ITS, UARTs, GPEX PCIe, SMMUv3, four Cadence GEM controllers, two DesignWare-derived MCI controllers, QSPI, I2C, xHCI, AHCI, a random generator, and the firmware-facing DDR and control regions. Unimplemented register windows remain visible to firmware without claiming unsupported behavior. Functional tests exercise both firmware and direct Linux boot on the Phytium Pi with an SDK Buildroot image. Manual testing covers Phytium Pi SD boot, COMe QSPI-to-SATA boot, all four CPUs, and network access. Known limitations are documented. In particular, the PBR handoff is a behavioral model validated against the available SDK firmware samples. Bin Meng (33): target/arm: Add Phytium FTC310 and FTC664 CPU models hw/arm: Add basic Phytium Pi machine hw/arm: phytium: Add Phytium E2000 PCIe host hw/sd: Add Synopsys DesignWare MCI controller hw/sd: Add Phytium E2000 MCI controller hw/arm: phytium: Connect Phytium E2000 MCI controllers tests/qtest: Add Synopsys DesignWare MCI coverage hw/arm: phytium: Connect Phytium E2000 GEM controllers hw/misc: Add Phytium E2000 DDR status hw/arm: phytium: Connect the Phytium E2000 DDR status hw/misc: Add Phytium E2000 MHU doorbell hw/arm: phytium: Connect the Phytium E2000 MHU hw/ssi: Add Phytium E2000 QSPI controller hw/arm: phytium: Connect the Phytium E2000 QSPI controller hw/misc: Add Phytium E2000 PBR model hw/arm: phytium: Integrate the Phytium E2000 PBR hw/arm: phytium: Add Phytium E2000 control region placeholders hw/misc: Support Phytium E2000 SCMI CPU power control hw/arm: phytium: Select the Phytium E2000 PBR boot medium hw/arm: phytium: Connect the Phytium E2000 I2C controller hw/arm: phytium: Add Phytium E2000 xHCI controllers hw/misc: Model the Phytium E2000 random generator hw/arm: phytium: Connect the Phytium E2000 random generator hw/arm: phytium: Support Phytium E2000 direct Linux boot hw/arm: phytium: Add Phytium E2000Q COMe machine hw/block: m25p80: Add GigaDevice GD25Q128 flash hw/arm: phytium: Connect the Phytium E2000Q COMe QSPI flash hw/arm: phytium: Add Phytium E2000 AHCI controllers hw/arm: Add Phytium E2000 Linux SCMI channel hw/arm: phytium: Connect the Phytium E2000 SMMUv3 docs/system/arm: Document Phytium E2000 machines tests/functional/aarch64: Add Phytium Pi boot tests MAINTAINERS: Add Phytium E2000Q machines MAINTAINERS | 17 + docs/system/arm/phytium_e2000.rst | 412 ++++++ docs/system/target-arm.rst | 1 + hw/arm/Kconfig | 22 + hw/arm/meson.build | 1 + hw/arm/phytium_e2000.c | 1181 ++++++++++++++++ hw/block/m25p80.c | 1 + hw/misc/meson.build | 4 + hw/misc/phytium_e2000_ddr.c | 197 +++ hw/misc/phytium_e2000_mhu.c | 818 +++++++++++ hw/misc/phytium_e2000_pbr.c | 1366 ++++++++++++++++++ hw/misc/phytium_e2000_rng.c | 182 +++ hw/sd/Kconfig | 5 + hw/sd/dw_mci.c | 1382 +++++++++++++++++++ hw/sd/meson.build | 2 + hw/sd/phytium_e2000_mci.c | 95 ++ hw/ssi/Kconfig | 5 + hw/ssi/meson.build | 1 + hw/ssi/phytium_qspi.c | 398 ++++++ include/hw/misc/phytium_e2000_ddr.h | 23 + include/hw/misc/phytium_e2000_mhu.h | 34 + include/hw/misc/phytium_e2000_pbr.h | 62 + include/hw/misc/phytium_e2000_rng.h | 23 + include/hw/sd/dw_mci.h | 74 + include/hw/sd/phytium_e2000_mci.h | 21 + include/hw/ssi/phytium_qspi.h | 23 + target/arm/tcg/cpu64.c | 81 ++ tests/functional/aarch64/meson.build | 2 + tests/functional/aarch64/test_phytium_pi.py | 77 ++ tests/qtest/dw_mci-test.c | 417 ++++++ tests/qtest/meson.build | 1 + 31 files changed, 6928 insertions(+) create mode 100644 docs/system/arm/phytium_e2000.rst create mode 100644 hw/arm/phytium_e2000.c create mode 100644 hw/misc/phytium_e2000_ddr.c create mode 100644 hw/misc/phytium_e2000_mhu.c create mode 100644 hw/misc/phytium_e2000_pbr.c create mode 100644 hw/misc/phytium_e2000_rng.c create mode 100644 hw/sd/dw_mci.c create mode 100644 hw/sd/phytium_e2000_mci.c create mode 100644 hw/ssi/phytium_qspi.c create mode 100644 include/hw/misc/phytium_e2000_ddr.h create mode 100644 include/hw/misc/phytium_e2000_mhu.h create mode 100644 include/hw/misc/phytium_e2000_pbr.h create mode 100644 include/hw/misc/phytium_e2000_rng.h create mode 100644 include/hw/sd/dw_mci.h create mode 100644 include/hw/sd/phytium_e2000_mci.h create mode 100644 include/hw/ssi/phytium_qspi.h create mode 100644 tests/functional/aarch64/test_phytium_pi.py create mode 100644 tests/qtest/dw_mci-test.c --- base-commit: 61d82640e03f5fdbeb70c455e2b3cbff539600ec branch: phytium -- 2.53.0