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envelope-from=bin.meng@processmission.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Instantiate QSPI0 at its command and direct-map windows so accesses from E2000 firmware reach the controller model. Signed-off-by: Bin Meng --- hw/arm/Kconfig | 1 + hw/arm/phytium_e2000.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 08128232ca..891d09e86b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -136,6 +136,7 @@ config PHYTIUM_E2000 select DW_MCI select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE + select PHYTIUM_E2000_QSPI select PL011 select SD select UNIMP diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c index ff8dd3354b..c6d789bb04 100644 --- a/hw/arm/phytium_e2000.c +++ b/hw/arm/phytium_e2000.c @@ -33,6 +33,7 @@ #include "hw/pci-host/gpex.h" #include "hw/sd/phytium_e2000_mci.h" #include "hw/sd/sd.h" +#include "hw/ssi/phytium_qspi.h" #include "net/net.h" #include "qobject/qlist.h" #include "qom/object.h" @@ -58,9 +59,11 @@ OBJECT_DECLARE_SIMPLE_TYPE(PhytiumE2000State, PHYTIUM_PI) #define PHYTIUM_E2000_GTIMER_HZ 50000000 enum { + PHYTIUM_E2000_QSPI_DIRECT, PHYTIUM_E2000_LOW_PERIPH, PHYTIUM_E2000_MCI0, PHYTIUM_E2000_MCI1, + PHYTIUM_E2000_QSPI_REGS, PHYTIUM_E2000_UART0, PHYTIUM_E2000_UART1, PHYTIUM_E2000_UART2, @@ -92,6 +95,7 @@ struct PhytiumE2000State { MachineState parent; struct arm_boot_info bootinfo; DeviceState *gic; + DeviceState *qspi; PhytiumE2000MciState *mci[PHYTIUM_E2000_NUM_MCIS]; CadenceGEMState *gem[PHYTIUM_E2000_NUM_GEMS]; MemoryRegion scp_sram; @@ -105,9 +109,11 @@ struct PhytiumE2000State { * handoff data and IACC is the fixed execution window for system firmware. */ static const MemMapEntry phytium_e2000_memmap[] = { + [PHYTIUM_E2000_QSPI_DIRECT] = { 0x00000000, 0x10000000 }, [PHYTIUM_E2000_LOW_PERIPH] = { 0x28000000, 0x00100000 }, [PHYTIUM_E2000_MCI0] = { 0x28000000, 0x00001000 }, [PHYTIUM_E2000_MCI1] = { 0x28001000, 0x00001000 }, + [PHYTIUM_E2000_QSPI_REGS] = { 0x28008000, 0x00001000 }, [PHYTIUM_E2000_UART0] = { 0x2800c000, 0x00001000 }, [PHYTIUM_E2000_UART1] = { 0x2800d000, 0x00001000 }, [PHYTIUM_E2000_UART2] = { 0x2800e000, 0x00001000 }, @@ -453,6 +459,18 @@ static void phytium_e2000_create_mci(PhytiumE2000State *s, int index) phytium_e2000_attach_sd_card(DW_MCI(mci), index); } +static void phytium_e2000_create_qspi(PhytiumE2000State *s) +{ + DeviceState *controller = qdev_new(TYPE_PHYTIUM_E2000_QSPI); + + s->qspi = controller; + sysbus_realize_and_unref(SYS_BUS_DEVICE(controller), &error_fatal); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(controller), 0, + phytium_e2000_memmap[PHYTIUM_E2000_QSPI_REGS].base, 2); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(controller), 1, + phytium_e2000_memmap[PHYTIUM_E2000_QSPI_DIRECT].base, 2); +} + static void phytium_e2000_create_ddr_status(PhytiumE2000State *s) { DeviceState *dev = qdev_new(TYPE_PHYTIUM_E2000_DDR); @@ -611,6 +629,8 @@ static void phytium_pi_init(MachineState *ms) phytium_e2000_create_ram(s); phytium_e2000_create_unimplemented(); + phytium_e2000_create_qspi(s); + phytium_e2000_create_cpus(s); phytium_e2000_create_gic(s); -- 2.53.0