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envelope-from=bin.meng@processmission.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Instantiate DesignWare-compatible I2C controller in the shared E2000 machine initialization and wire its documented interrupt. Leave board-specific I2C slave devices unmodeled. Signed-off-by: Bin Meng --- hw/arm/Kconfig | 1 + hw/arm/phytium_e2000.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 891d09e86b..7edf1bcb21 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -133,6 +133,7 @@ config PHYTIUM_E2000 imply PCI_DEVICES select ARM_GIC select CADENCE + select DESIGNWARE_I2C select DW_MCI select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c index fe362dd4bd..8194afb6c3 100644 --- a/hw/arm/phytium_e2000.c +++ b/hw/arm/phytium_e2000.c @@ -27,6 +27,7 @@ #include "hw/core/qdev-properties.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" +#include "hw/i2c/designware_i2c.h" #include "hw/misc/phytium_e2000_ddr.h" #include "hw/misc/phytium_e2000_mhu.h" #include "hw/misc/phytium_e2000_pbr.h" @@ -78,6 +79,7 @@ enum { PHYTIUM_E2000_UART4, PHYTIUM_E2000_UART5, PHYTIUM_E2000_UART6, + PHYTIUM_E2000_I2C, PHYTIUM_E2000_CLK_CTRL, PHYTIUM_E2000_SYSTEM_CTRL, PHYTIUM_E2000_GIC_DIST, @@ -141,6 +143,7 @@ static const MemMapEntry phytium_e2000_memmap[] = { [PHYTIUM_E2000_UART3] = { 0x2800f000, 0x00001000 }, [PHYTIUM_E2000_UART4] = { 0x28014000, 0x00001000 }, [PHYTIUM_E2000_UART5] = { 0x2802a000, 0x00001000 }, + [PHYTIUM_E2000_I2C] = { 0x28030000, 0x00001000 }, [PHYTIUM_E2000_UART6] = { 0x28032000, 0x00001000 }, [PHYTIUM_E2000_CLK_CTRL] = { 0x28100000, 0x00001000 }, [PHYTIUM_E2000_SYSTEM_CTRL] = { 0x30000000, 0x00001000 }, @@ -182,6 +185,8 @@ static const int phytium_e2000_uart_irqmap[] = { [6] = 107, }; +static const int phytium_e2000_i2c_irq = 106; + static const uint8_t phytium_e2000_gem_num_queues[] = { 8, 4, 4, 4 }; static const int phytium_e2000_gem_irqmap[PHYTIUM_E2000_NUM_GEMS] @@ -328,6 +333,19 @@ static void phytium_e2000_create_uart(PhytiumE2000State *s, int index) qdev_get_gpio_in(s->gic, phytium_e2000_uart_irqmap[index])); } +static void phytium_e2000_create_i2c(PhytiumE2000State *s) +{ + DeviceState *dev = qdev_new(TYPE_DESIGNWARE_I2C); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + object_property_add_child(OBJECT(s), "i2c", OBJECT(dev)); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map_overlap(sbd, 0, + phytium_e2000_memmap[PHYTIUM_E2000_I2C].base, 1); + sysbus_connect_irq(sbd, 0, + qdev_get_gpio_in(s->gic, phytium_e2000_i2c_irq)); +} + static void phytium_e2000_create_gem(PhytiumE2000State *s, int index) { DeviceState *dev = qdev_new(TYPE_CADENCE_GEM); @@ -801,6 +819,7 @@ static void phytium_e2000_init(MachineState *ms) for (i = 0; i < PHYTIUM_E2000_NUM_UARTS; i++) { phytium_e2000_create_uart(s, i); } + phytium_e2000_create_i2c(s); for (i = 0; i < PHYTIUM_E2000_NUM_GEMS; i++) { phytium_e2000_create_gem(s, i); } -- 2.53.0