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envelope-from=bin.meng@processmission.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The vendor device tree routes PCIe DMA through an Arm SMMUv3, but its MMIO range currently reaches an unimplemented placeholder. Linux therefore reports that the IOMMU has no translation support. Attach the generic SMMUv3 model to the GPEX root bus with the documented interrupt wiring and document stage-1 DMA translation support. Signed-off-by: Bin Meng --- hw/arm/Kconfig | 1 + hw/arm/phytium_e2000.c | 39 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 11c16bbebc..ea16a8b3f4 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -133,6 +133,7 @@ config PHYTIUM_E2000 imply PCI_DEVICES select AHCI_SYSBUS select ARM_GIC + select ARM_SMMUV3 select CADENCE select DESIGNWARE_I2C select DW_MCI diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c index cfd1ca70c9..8ffd566b36 100644 --- a/hw/arm/phytium_e2000.c +++ b/hw/arm/phytium_e2000.c @@ -22,6 +22,7 @@ #include "hw/arm/boot.h" #include "hw/arm/bsa.h" #include "hw/arm/machines-qom.h" +#include "hw/arm/smmuv3.h" #include "hw/block/flash.h" #include "hw/char/pl011.h" #include "hw/core/boards.h" @@ -69,6 +70,7 @@ OBJECT_DECLARE_TYPE(PhytiumE2000State, PhytiumE2000MachineClass, #define PHYTIUM_E2000_NUM_SATA_PORTS 1 #define PHYTIUM_E2000_SATA_BOOT_AHCI 1 #define PHYTIUM_E2000_NUM_GEMS 4 +#define PHYTIUM_E2000_NUM_SMMU_IRQS 4 #define PHYTIUM_E2000_MHU_BASE 0x32a00000 #define PHYTIUM_E2000_SCP_SRAM_BASE 0x32a10000 @@ -212,6 +214,14 @@ static const int phytium_e2000_uart_irqmap[] = { static const int phytium_e2000_i2c_irq = 106; +/* Keep the architectural SMMUv3 output order aligned with the vendor DT */ +static const int phytium_e2000_smmu_irqmap[] = { + [SMMU_IRQ_EVTQ] = 240, + [SMMU_IRQ_PRIQ] = 239, + [SMMU_IRQ_CMD_SYNC] = 236, + [SMMU_IRQ_GERROR] = 242, +}; + static const int phytium_e2000_xhci_irqmap[] = { [0] = 16, [1] = 17, @@ -472,7 +482,7 @@ static int phytium_e2000_pcie_map_irq(PCIDevice *pdev, int pin) return pin; } -static void phytium_e2000_create_pcie(PhytiumE2000State *s) +static PCIBus *phytium_e2000_create_pcie(PhytiumE2000State *s) { DeviceState *dev = qdev_new(TYPE_GPEX_HOST); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -546,6 +556,29 @@ static void phytium_e2000_create_pcie(PhytiumE2000State *s) qdev_get_gpio_in(s->gic, phytium_e2000_pcie_irqmap[i])); gpex_set_irq_num(GPEX_HOST(dev), i, phytium_e2000_pcie_irqmap[i]); } + + return PCI_HOST_BRIDGE(dev)->bus; +} + +static void phytium_e2000_create_smmu(PhytiumE2000State *s, PCIBus *bus) +{ + DeviceState *dev = qdev_new(TYPE_ARM_SMMUV3); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + int i; + + object_property_add_child(OBJECT(s), "smmu", OBJECT(dev)); + object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), + &error_abort); + object_property_set_link(OBJECT(dev), "memory", + OBJECT(get_system_memory()), &error_abort); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map_overlap(sbd, 0, + phytium_e2000_memmap[PHYTIUM_E2000_SYSTEM_CTRL].base, 2); + + for (i = 0; i < PHYTIUM_E2000_NUM_SMMU_IRQS; i++) { + sysbus_connect_irq(sbd, i, + qdev_get_gpio_in(s->gic, phytium_e2000_smmu_irqmap[i])); + } } static void phytium_e2000_reject_legacy_firmware( @@ -951,6 +984,7 @@ static void phytium_e2000_init(MachineState *ms) PhytiumE2000MachineClass *pemc = PHYTIUM_E2000_MACHINE_GET_CLASS(ms); bool firmware_loaded; + PCIBus *pcie_bus; int i; if (kvm_enabled()) { @@ -1020,7 +1054,8 @@ static void phytium_e2000_init(MachineState *ms) phytium_e2000_create_gem(s, i); } - phytium_e2000_create_pcie(s); + pcie_bus = phytium_e2000_create_pcie(s); + phytium_e2000_create_smmu(s, pcie_bus); s->bootinfo.ram_size = ms->ram_size; s->bootinfo.board_id = -1; -- 2.53.0