From: sashiko-bot@kernel.org
To: "Biju Das" <biju.das.jz@bp.renesas.com>
Cc: linux-pci@vger.kernel.org, wsa+renesas@sang-engineering.com
Subject: Re: [PATCH v2 2/2] PCI: rzg3s-host: Add support for RZ/G3L SoC
Date: Thu, 03 Sep 2026 13:41:52 +0000 [thread overview]
Message-ID: <20260903134153.240D01F00A3D@smtp.kernel.org> (raw)
In-Reply-To: <20260903133320.144245-3-biju.das.jz@bp.renesas.com>
> Add SoC-specific data for the RZ/G3L (R9A08G046) PCIe controller and
> register its "renesas,r9a08g046-pcie" compatible string. RZ/G3L reuses
> the RZ/G3E config init/deinit callbacks and power resets, with its own
> L1-allow syscon offset and mask.
>
> Also increase the timeout in rzg3s_pcie_set_max_link_speed() to fix
> the "Failed to set max link speed" message seen on RZ/G3L.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260903133320.144245-1-biju.das.jz@bp.renesas.com?part=2
next prev parent reply other threads:[~2026-09-03 13:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 13:33 [PATCH v2 0/2] Add RZ/G3L PCIe support Biju Das
2026-09-03 13:33 ` [PATCH v2 1/2] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3L SoC Biju Das
2026-09-03 13:38 ` sashiko-bot
2026-09-03 14:36 ` Geert Uytterhoeven
2026-09-11 7:11 ` Krzysztof Kozlowski
2026-09-03 13:33 ` [PATCH v2 2/2] PCI: rzg3s-host: Add support for " Biju Das
2026-09-03 13:41 ` sashiko-bot [this message]
2026-09-11 8:16 ` [PATCH v2 0/2] Add RZ/G3L PCIe support Manivannan Sadhasivam
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