From: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: himal.prasad.ghimiray@intel.com, arvind.yadav@intel.com,
tejas.upadhyay@intel.com,
Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
Subject: [PATCH v3 3/7] drm/xe/guc: Print register addresses in capture snapshot output
Date: Thu, 3 Sep 2026 19:48:30 +0530 [thread overview]
Message-ID: <20260903141834.1315675-4-naresh.kumar.g@intel.com> (raw)
In-Reply-To: <20260903141834.1315675-1-naresh.kumar.g@intel.com>
Include register offsets in GuC capture snapshot print output for both
32-bit and 64-bit registers.
When dumping captured engine register state, print each register name
alongside its MMIO offset to make the snapshot output easier to
cross-reference with register definitions and hardware debug
documentation.
This improves postmortem analysis without changing capture contents.
v2:(Sashiko)
- Ensure lower DWORD prints
v3:(Sashiko)
- Use the LOW_DW MMIO offset(capture in last_address) when combined 64bit
register values in the dump instead of HI_SW offset
- preserve existing coredump register-name format and append register
address as trailing metadata as a debug info and avoids disrupting
existing format
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/xe_guc_capture.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c
index 82df19b304e1..53171cf5e8b6 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.c
+++ b/drivers/gpu/drm/xe/xe_guc_capture.c
@@ -1716,6 +1716,7 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
struct xe_devcoredump_snapshot *devcore_snapshot = &devcoredump->snapshot;
struct gcap_reg_list_info *reginfo = NULL;
u32 i, last_value = 0;
+ u32 last_address = 0;
bool low32_ready = false;
if (!list || !list->list || list->num_regs == 0)
@@ -1743,6 +1744,7 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
switch (reg_desc->data_type) {
case REG_64BIT_LOW_DW:
last_value = value;
+ last_address = reg_desc->reg.addr;
/*
* A 64 bit register define requires 2 consecutive
@@ -1774,7 +1776,11 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
XE_WARN_ON(!low32_ready);
low32_ready = false;
- drm_printf(p, "\t%s: 0x%016llx\n", reg_desc->regname, value_qw);
+ drm_printf(p, "\t%s: 0x%016llx [addr=0x%x]\n",
+ reg_desc->regname,
+ value_qw,
+ last_address);
+
break;
}
@@ -1788,10 +1794,14 @@ snapshot_print_by_list_order(struct xe_hw_engine_snapshot *snapshot, struct drm_
XE_WARN_ON(low32_ready);
if (FIELD_GET(GUC_REGSET_STEERING_NEEDED, reg_desc->flags))
- drm_printf(p, "\t%s[%u]: 0x%08x\n", reg_desc->regname,
- reg_desc->dss_id, value);
+ drm_printf(p, "\t%s[%u]: 0x%08x [addr=0x%x]\n",
+ reg_desc->regname,
+ reg_desc->dss_id, value, reg_desc->reg.addr);
+
else
- drm_printf(p, "\t%s: 0x%08x\n", reg_desc->regname, value);
+ drm_printf(p, "\t%s: 0x%08x [addr=0x%x]\n",
+ reg_desc->regname, value, reg_desc->reg.addr);
+
break;
}
--
2.43.0
next prev parent reply other threads:[~2026-09-03 14:19 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-03 14:18 [PATCH v3 0/7] drm/xe: Capture additional HW register state in devcoredump Nareshkumar Gollakoti
2026-09-03 14:18 ` [PATCH v3 1/7] drm/xe/devcoredump: Capture GT fuse registers " Nareshkumar Gollakoti
2026-09-03 14:32 ` sashiko-bot
2026-09-03 14:18 ` [PATCH v3 2/7] drm/xe/devcoredump: Add GuC register snapshot to devcoredump Nareshkumar Gollakoti
2026-09-03 14:18 ` Nareshkumar Gollakoti [this message]
2026-09-03 14:18 ` [PATCH v3 4/7] drm/xe: dump GAM page fault report registers in devcoredump Nareshkumar Gollakoti
2026-09-03 14:18 ` [PATCH v3 5/7] drm/xe/guc: add TDL, SLICE gfx registers to capture list Nareshkumar Gollakoti
2026-09-03 14:18 ` [PATCH v3 6/7] drm/xe: capture L3 node status registers in devcoredump Nareshkumar Gollakoti
2026-09-03 14:18 ` [PATCH v3 7/7] drm/xe/guc: capture additional engine state registers Nareshkumar Gollakoti
2026-09-03 14:33 ` sashiko-bot
2026-09-03 14:54 ` ✗ CI.checkpatch: warning for drm/xe: Capture additional HW register state in devcoredump (rev3) Patchwork
2026-09-03 14:56 ` ✓ CI.KUnit: success " Patchwork
2026-09-03 15:39 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-04 2:01 ` ✗ Xe.CI.FULL: failure " Patchwork
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