From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 233EAC79F80 for ; Thu, 3 Sep 2026 20:10:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8AC1B10F76D; Thu, 3 Sep 2026 20:10:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="asHUNgEA"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 41E8710E52F for ; Thu, 3 Sep 2026 20:10:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788466238; x=1820002238; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=dJ23TjJwGFqAUHr7Ar4X9qnZRf9dv9fdIiDiNuk2Zqc=; b=asHUNgEALVVt5tu1mBjCWYZOTbV2I9qDin7QnW/UMdBlOgKLdsGQsco8 6tZNu4NPw8jGNirAZsGTzaxD9QWHc8bfGPoF2o8x1ZqSvynFn9ODw6wlw 22SO33M3OEFJHrLkBKdB4kntHzB09JXt0KhsuNbqNEIp/efX1B1sVaZgV aLwFGuCGB/5JdNGMlrGrCZCgCul30sR6d93R8LKDMfU7tcKlrN1rYghBr piOlegmt5cXEwEC7UIeHWRpmxx0qMoz373qce0gYK9NTHxS7bLpps4RKO H7VU0QjspGJXWct1brTWJ1P7iNp6E4wJQxPqlbkkjhA10OsEJ8r2UPsnx g==; X-CSE-ConnectionGUID: MpssD7YFSFaOzoxOF03+mw== X-CSE-MsgGUID: a0/XTk7oTTuqBBn6dA2bcw== X-IronPort-AV: E=McAfee;i="6800,10657,11895"; a="88994639" X-IronPort-AV: E=Sophos;i="6.25,260,1779174000"; d="scan'208";a="88994639" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2026 13:10:37 -0700 X-CSE-ConnectionGUID: SHTISy7IQJmVtoh3HQr45A== X-CSE-MsgGUID: QzV5bgCFQSGpgXVTSBRmsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,260,1779174000"; d="scan'208";a="273348152" Received: from mjruhl-vm.amr.corp.intel.com ([10.11.186.166]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2026 13:10:33 -0700 From: "Michael J. Ruhl" To: platform-driver-x86@vger.kernel.org, intel-xe@lists.freedesktop.org, hansg@kernel.org, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com, rodrigo.vivi@intel.com, thomas.hellstrom@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, david.e.box@linux.intel.com, anoop.c.vijay@intel.com, badal.nilawar@intel.com, matthew.d.roper@intel.com, james.ausmus@intel.com, karthik.poosa@intel.com Subject: [PATCH v5 14/18] drm/xe/vsec: Crescent Island PMT callbacks Date: Thu, 3 Sep 2026 13:10:16 -0700 Message-ID: <20260903201002.1064889-34-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260903201002.1064889-20-michael.j.ruhl@intel.com> References: <20260903201002.1064889-20-michael.j.ruhl@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" CRI PMT support requires callbacks to access the discovery status and control areas. Access is a common MMIO area that requires an index to be set before access is allowed. Introduce the necessary callbacks to get the status and control information for CRI PMT usage. Add the glue logic to register the CRI PMT functionality. Signed-off-by: Michael J. Ruhl --- drivers/gpu/drm/xe/xe_vsec.c | 108 ++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c index 0438810337dd..336c4b7d284b 100644 --- a/drivers/gpu/drm/xe/xe_vsec.c +++ b/drivers/gpu/drm/xe/xe_vsec.c @@ -355,17 +355,110 @@ int xe_pmt_telem_read(struct device *dev, u32 guid, u64 *data, loff_t user_offse return ret == 0 ? count : ret; } -static struct pmt_callbacks xe_pmt_cb = { +/** + * xe_pmt_read_reg() - read a crashlog register + * @dev: the xe device that registered the callback + * @guid: PMT guid of the crashlog instance + * @reg: data read from the PMT data structure + * @offset: which data to read from the PMT data structure + * + * Read the requested PMT register based on the pcie device and guid. The + * supported struct is the Crashlog Type1 Version2. + * + * Currently this is for CRI only. + */ +static int xe_pmt_read_reg(struct device *dev, u32 guid, u32 *reg, u32 offset) +{ + struct xe_device *xe = kdev_to_xe_device(dev); + void __iomem *disc_addr = xe->mmio.regs + xe->pmt.base_offset; + int ret = 0; + u32 inst; + int idx; + + if (!drm_dev_enter(&xe->drm, &idx)) + return -ENODEV; + + if (FIELD_GET(GUID_DEVICE_ID, guid) != CRI_DEVICE_ID || + FIELD_GET(GUID_CAP_TYPE, guid) != CRASHLOG) { + ret = -EINVAL; + goto dev_exit; + } + + inst = FIELD_GET(GUID_RECORD_ID, guid) == PUNIT ? + CRI_CRASHLOG_PUNIT_DISC_OFFSET : CRI_CRASHLOG_OOBMSM_DISC_OFFSET; + disc_addr += inst + offset; + + xe_pm_runtime_get(xe); + mutex_lock(&xe->pmt.lock); + + xe->soc_remapper.set_telem_region(xe, CRI_IDX_TELEM_DISCOVERY); + + memcpy_fromio(reg, disc_addr, sizeof(*reg)); + + mutex_unlock(&xe->pmt.lock); + xe_pm_runtime_put(xe); + +dev_exit: + drm_dev_exit(idx); + + return ret; +} + +static int xe_pmt_write_reg(struct device *dev, u32 guid, u32 reg, u32 offset) +{ + struct xe_device *xe = kdev_to_xe_device(dev); + void __iomem *disc_addr = xe->mmio.regs + xe->pmt.base_offset; + int ret = 0; + u32 inst; + int idx; + + if (!drm_dev_enter(&xe->drm, &idx)) + return -ENODEV; + + if (FIELD_GET(GUID_DEVICE_ID, guid) != CRI_DEVICE_ID || + FIELD_GET(GUID_CAP_TYPE, guid) != CRASHLOG) { + ret = -EINVAL; + goto dev_exit; + } + + inst = FIELD_GET(GUID_RECORD_ID, guid) == PUNIT ? + CRI_CRASHLOG_PUNIT_DISC_OFFSET : CRI_CRASHLOG_OOBMSM_DISC_OFFSET; + disc_addr += inst + offset; + + xe_pm_runtime_get(xe); + mutex_lock(&xe->pmt.lock); + + xe->soc_remapper.set_telem_region(xe, CRI_IDX_TELEM_DISCOVERY); + + memcpy_toio(disc_addr, ®, sizeof(reg)); + + mutex_unlock(&xe->pmt.lock); + xe_pm_runtime_put(xe); + +dev_exit: + drm_dev_exit(idx); + + return ret; +} + +static struct pmt_callbacks xe_bmg_pmt_cb = { .read_telem = xe_pmt_telem_read, }; +static struct pmt_callbacks xe_cri_pmt_cb = { + .read_telem = xe_pmt_telem_read, + .read_reg = xe_pmt_read_reg, + .write_reg = xe_pmt_write_reg, +}; + static const int vsec_platforms[] = { [XE_BATTLEMAGE] = XE_VSEC_BMG, + [XE_CRESCENTISLAND] = XE_VSEC_CRI, }; static enum xe_vsec get_platform_info(struct xe_device *xe) { - if (xe->info.platform > XE_BATTLEMAGE) + if (xe->info.platform > XE_CRESCENTISLAND) return XE_VSEC_UNKNOWN; return vsec_platforms[xe->info.platform]; @@ -395,8 +488,17 @@ void xe_vsec_init(struct xe_device *xe) if (IS_SRIOV_VF(xe)) return; xe->pmt.base_offset = BMG_TELEMETRY_OFFSET; - info->priv_data = &xe_pmt_cb; + info->priv_data = &xe_bmg_pmt_cb; break; + + case XE_VSEC_CRI: + if (IS_SRIOV_VF(xe)) + return; + xe->pmt.base_offset = CRI_PMT_OFFSET; + info->priv_data = &xe_cri_pmt_cb; + xe->soc_remapper.set_telem_region(xe, CRI_IDX_TELEM_DISCOVERY); + break; + default: break; } -- 2.43.0