From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2DB7C61DD3 for ; Fri, 4 Sep 2026 02:22:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 769C110F82D; Fri, 4 Sep 2026 02:22:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="anbBaOJJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7925310F81B for ; Fri, 4 Sep 2026 02:22:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788488536; x=1820024536; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=tFV2D7I5QQ1QVytaaVZ+afHw01cS7wg6UiF5jPNAkFY=; b=anbBaOJJ50UKmbhMTEYgprluhZw6//QFFDt4RtQ0jIphqcTuUG3+JpTP GyWHRHKh3Pt7F/UqL4xJ5SpTdBFjXrqTJP2brI4V8l8eTn74fQgkIM3qZ 2ROpNrupppN8AxV9ua4KQqDKOjt3jSV/gtB8QqnPn2Ht9aqHEzRCrDFg1 Z2+CLIzuv+MnYy3Za6giAwton9ftB5uDmlcbHDnOx5hBSKiKEFnih7HEn /uLbMq1SmL6p8CQUSn/geis6jINTrkiZs4sddu6MwZibXicvnTYmKqmJN Sv2Bz+ZkLH1o/s1XS+q6y4MRZ+phQ1JeHu3H5xz79hFRui/HEhrZDFiFb A==; X-CSE-ConnectionGUID: 8Hbhyl0TRg2wPHtYwwnNsQ== X-CSE-MsgGUID: IDaKQh5KQKmKLdJ4IoS48w== X-IronPort-AV: E=McAfee;i="6800,10657,11895"; a="106506290" X-IronPort-AV: E=Sophos;i="6.25,260,1779174000"; d="scan'208";a="106506290" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2026 19:22:15 -0700 X-CSE-ConnectionGUID: 3KsCAjOjRti6GYP/fWbnzg== X-CSE-MsgGUID: pbCGoEliQx2a3cXKSXte8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,260,1779174000"; d="scan'208";a="275185135" Received: from gsse-cloud1.jf.intel.com ([10.54.39.91]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2026 19:22:15 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org Subject: [PATCH v5 18/25] drm/xe: Add xe_hw_engine_write_ring_tail Date: Thu, 3 Sep 2026 19:22:00 -0700 Message-Id: <20260904022207.3490018-19-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260904022207.3490018-1-matthew.brost@intel.com> References: <20260904022207.3490018-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" ULLS for migration jobs need to directly set hw engine ring tail, add function to support this. Signed-off-by: Matthew Brost Link: https://patch.msgid.link/20260228013501.106680-19-matthew.brost@intel.com Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/xe/xe_hw_engine.c | 20 ++++++++++++++++++++ drivers/gpu/drm/xe/xe_hw_engine.h | 1 + 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 010499766fce..635744f79be6 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -282,6 +282,26 @@ static void hw_engine_fini(void *arg) hwe->gt = NULL; } +static void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val) +{ + xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); + xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); + + reg.addr += hwe->mmio_base; + + xe_mmio_write32(&hwe->gt->mmio, reg, val); +} + +/** + * xe_hw_engine_write_ring_tail() - Write ring tail + * @hwe: engine + * @val: desired 32-bit value to write + */ +void xe_hw_engine_write_ring_tail(struct xe_hw_engine *hwe, u32 val) +{ + xe_hw_engine_mmio_write32(hwe, RING_TAIL(0), val); +} + /** * xe_hw_engine_mmio_read32() - Read engine register * @hwe: engine diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h index c3ee37f8cfc0..e13610a56ad7 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.h +++ b/drivers/gpu/drm/xe/xe_hw_engine.h @@ -77,5 +77,6 @@ u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe); enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe); u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg); +void xe_hw_engine_write_ring_tail(struct xe_hw_engine *hwe, u32 val); #endif -- 2.34.1