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Thu, 03 Sep 2026 22:54:15 -0700 (PDT) From: Magnus Lindholm To: davem@davemloft.net, andreas@gaisler.com Cc: sam@ravnborg.org, sparclinux@vger.kernel.org, linux-kernel@vger.kernel.org, Magnus Lindholm Subject: [PATCH 2/2] sparc32: synchronize SuperSPARC instruction updates Date: Fri, 4 Sep 2026 07:53:06 +0200 Message-ID: <20260904055359.327050-3-linmag7@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260904055359.327050-1-linmag7@gmail.com> References: <20260904055359.327050-1-linmag7@gmail.com> Precedence: bulk X-Mailing-List: sparclinux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit SuperSPARC keeps its instruction cache coherent by snooping bus transactions, but a FLUSH is still required after modifying instructions. It drains the local store buffer, completes pending coherency traffic and clears the local pipeline and instruction buffer. FLUSH affects only the processor which executes it. The SuperSPARC II addendum also states that the store buffer cannot be snooped. The writer's FLUSH is therefore required to make buffered stores reach the coherent hierarchy before remote processors clear their own pipelines. Implement the previously empty Viking signal-instruction operation and stop bypassing the SMP wrapper. Run a local FLUSH on the writing CPU before asking remote processors to clear their pipelines. Also implement the generic flush_icache_range() hook for Viking. The module loader and kernel text modification paths use this hook after publishing executable code. One FLUSH on each processor is sufficient: Viking invalidates instruction-cache entries through hardware snooping, while FLUSH provides the required store and pipeline synchronization. The manual is explicit that FLUSH is not scoped to the address given to it: "No cached information is explicitly flushed by the instruction ... FLUSH operations simply cause an exact synchronization of all pending activity" (section 7.4). A single FLUSH per processor therefore covers however many words were written before it, which is also why the sig_insns hook above needs only one FLUSH for its two-instruction trampoline. This follows SuperSPARC Family User's Manual sections 7.4, Flush (IFLUSH), and 10.2.5, Instruction Cache Consistency, and SuperSPARC II Addendum section A.8.2, Store Buffer & Snoops. Signed-off-by: Magnus Lindholm --- arch/sparc/include/asm/cacheflush_32.h | 2 +- arch/sparc/mm/srmmu.c | 32 ++++++++++++++++++++++++-- arch/sparc/mm/viking.S | 4 ++++ 3 files changed, 35 insertions(+), 3 deletions(-) diff --git a/arch/sparc/include/asm/cacheflush_32.h b/arch/sparc/include/asm/cacheflush_32.h index 9fee0ccfccb8..4249663efacc 100644 --- a/arch/sparc/include/asm/cacheflush_32.h +++ b/arch/sparc/include/asm/cacheflush_32.h @@ -15,7 +15,7 @@ sparc32_cachetlb_ops->cache_range(vma, start, end) #define flush_cache_page(vma,addr,pfn) \ sparc32_cachetlb_ops->cache_page(vma, addr) -#define flush_icache_range(start, end) do { } while (0) +void flush_icache_range(unsigned long start, unsigned long end); #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ do { \ diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index 3b87e6f53fca..2cf26285e50f 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c @@ -1816,9 +1816,12 @@ static void smp_flush_page_to_ram(unsigned long page) static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) { + preempt_disable(); + /* Publish the stores before remote CPUs discard prefetched insns. */ + local_ops->sig_insns(mm, insn_addr); if (any_other_mm_cpus(mm)) xc2(local_ops->sig_insns, (unsigned long)mm, insn_addr); - local_ops->sig_insns(mm, insn_addr); + preempt_enable(); } static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = { @@ -1836,6 +1839,32 @@ static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = { }; #endif +static void local_viking_flush_icache_range(unsigned long start, + unsigned long end) +{ + if (start >= end) + return; + + /* Viking snoops the I-cache; FLUSH drains stores and the pipeline. */ + __asm__ __volatile__("flush %0" : : "r" (start) : "memory"); +} + +void flush_icache_range(unsigned long start, unsigned long end) +{ + if (start >= end || poke_srmmu != poke_viking) + return; + + /* Keep the locally flushed CPU as the CPU omitted by the cross-call. */ + preempt_disable(); + /* Make the modified instructions visible before flushing remotes. */ + local_viking_flush_icache_range(start, end); +#ifdef CONFIG_SMP + xc2(local_viking_flush_icache_range, start, end); +#endif + preempt_enable(); +} +EXPORT_SYMBOL(flush_icache_range); + /* Load up routines and constants for sun4m and sun4d mmu */ void __init load_mmu(void) { @@ -1868,7 +1897,6 @@ void __init load_mmu(void) smp_cachetlb_ops.cache_page = local_ops->cache_page; smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram; - smp_cachetlb_ops.sig_insns = local_ops->sig_insns; smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma; } diff --git a/arch/sparc/mm/viking.S b/arch/sparc/mm/viking.S index 8b4e251bbba2..f8cdd399d26b 100644 --- a/arch/sparc/mm/viking.S +++ b/arch/sparc/mm/viking.S @@ -201,7 +201,11 @@ viking_flush_tlb_page: viking_flush_page_to_ram: viking_flush_page_for_dma: + retl + nop + viking_flush_sig_insns: + flush %o1 retl nop -- 2.43.0