Re: [PATCH] drm/i915/display: Limit SEL_FETCH clear to supported pipes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch adds a check to prevent unclaimed register accesses for uninstantiated SEL_FETCH registers, but incorrectly limits this check strictly to Display Ver 12, leaving Ver 13+ platforms vulnerable.
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commit 5a2a4e5321d7248032644f135d53b64d20ede511
Author: Nemesa Garg <nemesa.garg@intel.com>

drm/i915/display: Limit SEL_FETCH clear to supported pipes

This patch adds checks to skip clearing SEL_FETCH_PLANE_CTL and
SEL_FETCH_CUR_CTL on pipes that do not implement these registers,
preventing unclaimed register accesses when disabling planes and cursors.

> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index cce041e1da51d..de4359cbe306d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -545,6 +545,10 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb,
>  	if (!HAS_PSR2_SEL_FETCH(display))
>  		return;
>  
> +	/* Display ver 12 only instantiates these registers for pipe A */
> +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> +		return;
> +

[Severity: Medium]
Does this check leave Display Ver 13+ platforms vulnerable to the same issue?

Because PSR2 is only supported on transcoders A and B on newer platforms
(like Alderlake P), the SEL_FETCH registers for pipes C and D are not
instantiated. 

With this check strictly limited to DISPLAY_VER(display) == 12, disabling a
cursor on pipe C or D on Ver 13+ will evaluate to false, bypass this
protection, and still cause an unclaimed register access.

>  	intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), 0);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 5cda1ab90e40f..252df30debc9b 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -893,6 +893,10 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb,
>  	if (!HAS_PSR2_SEL_FETCH(display))
>  		return;
>  
> +	/* Display ver 12 only instantiates these registers for pipe A */
> +	if (DISPLAY_VER(display) == 12 && pipe != PIPE_A)
> +		return;
> +

[Severity: Medium]
Similarly for planes, does limiting this check to exactly Ver 12 allow
unclaimed register accesses on Ver 13+?

Disabling a plane on pipe C or D on a Display Ver 13+ platform will also bypass
this check and attempt to write to uninstantiated SEL_FETCH registers.

>  	intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
>  }
>

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Sashiko AI review · https://sashiko.dev/#/patchset/20260904062744.3010375-1-nemesa.garg@intel.com?part=1