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[79.129.254.8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cf75ce49esm86698155e9.1.2026.09.04.00.29.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 00:29:11 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com, =?UTF-8?q?Christian=20K=C3=B6nig?= , Natalie Vock , Tvrtko Ursulin , Felix Kuehling , Lijo Lazar Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 8/8] drm/amdgpu/sdma: Use common SDMA legacy queue reset on SDMA v4.4.2 Date: Fri, 4 Sep 2026 09:28:50 +0200 Message-ID: <20260904072850.321759-9-timur.kristof@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260904072850.321759-1-timur.kristof@gmail.com> References: <20260904072850.321759-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Now, sdma_v4_4_2_reset_queue() does basically the same as amdgpu_sdma_reset_queue_legacy() so let's use that. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 796ea9f74763..60bb22d0a43b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1574,20 +1574,6 @@ static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, - unsigned int vmid, - struct amdgpu_fence *timedout_fence) -{ - struct amdgpu_device *adev = ring->adev; - u32 id = ring->me; - int r; - - amdgpu_amdkfd_suspend(adev, true); - r = amdgpu_sdma_reset_engine(adev, id); - amdgpu_amdkfd_resume(adev, true); - return r; -} - static int sdma_v4_4_2_stop_queue(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -2031,7 +2017,7 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = { .emit_wreg = sdma_v4_4_2_ring_emit_wreg, .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, - .reset = sdma_v4_4_2_reset_queue, + .reset = amdgpu_sdma_reset_queue_legacy, }; static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { @@ -2063,7 +2049,7 @@ static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = { .emit_wreg = sdma_v4_4_2_ring_emit_wreg, .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait, .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, - .reset = sdma_v4_4_2_reset_queue, + .reset = amdgpu_sdma_reset_queue_legacy, }; static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev) -- 2.55.0