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[211.23.39.77]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c397b1sm9356695a91.8.2026.09.04.00.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 00:56:36 -0700 (PDT) From: Jason Yang To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: Michael Riesch , Sebastian Reichel , Bryan O'Donoghue , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang Subject: [RFC PATCH] arm64: dts: rockchip: add mipi csi-2 receiver nodes for the dcphys on rk3588 Date: Fri, 4 Sep 2026 15:55:34 +0800 Message-ID: <20260904075534.574037-1-jason98166@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <8e10a8c0-3648-47b5-9131-a1abdd7eb8c5@kernel.org> References: <8e10a8c0-3648-47b5-9131-a1abdd7eb8c5@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260904_005639_139200_6EDE5C55 X-CRM114-Status: GOOD ( 11.65 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This is test patch, contains the following 3 changes: - raise #phy-cells to 2 - add PHY_TYPE_DSI to the dsi nodes - add mipi csi0 and csi1 Signed-off-by: Jason Yang --- Hi Michael, Krzysztof, Here is the test patch for https://lore.kernel.org/r/20260821-dcphy-rx-v1-v4-0-f1797634233d@gmail.com I have tested imx219/ov5640 stream with csi0 and meanwhile stream on rpi panel with dsi0, both using mipidcphy0. Related commits: 2e177b85541d ("arm64: dts: rockchip: add mipi dcphy nodes to rk3588") 0d0947766d87 ("arm64: dts: rockchip: add dsi controller nodes on rk3588") 5052c99cf052 ("arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588") Best regards, Jason arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 76 ++++++++++++++++++- 1 file changed, 72 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index fc1fdbfd3162..dd2bbc02f8d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1516,10 +1516,18 @@ vicap_dvp: port@0 { vicap_mipi0: port@1 { reg = <0x1>; + + vicap_mipi0_input: endpoint { + remote-endpoint = <&csi0_output>; + }; }; vicap_mipi1: port@2 { reg = <0x2>; + + vicap_mipi1_input: endpoint { + remote-endpoint = <&csi1_output>; + }; }; vicap_mipi2: port@3 { @@ -1568,6 +1576,66 @@ vicap_mmu: iommu@fdce0800 { status = "disabled"; }; + csi0: csi@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd10000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_0>; + phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_TYPE_CSI>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_in: port@0 { + reg = <0>; + }; + + csi0_out: port@1 { + reg = <1>; + + csi0_output: endpoint { + remote-endpoint = <&vicap_mipi0_input>; + }; + }; + }; + }; + + csi1: csi@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd20000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_1>; + phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_TYPE_CSI>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_in: port@0 { + reg = <0>; + }; + + csi1_out: port@1 { + reg = <1>; + + csi1_output: endpoint { + remote-endpoint = <&vicap_mipi1_input>; + }; + }; + }; + }; + csi2: csi@fdd30000 { compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdd30000 0x0 0x10000>; @@ -1788,7 +1856,7 @@ dsi0: dsi@fde20000 { resets = <&cru SRST_P_DSIHOST0>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipidcphy0 PHY_TYPE_DPHY>; + phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_TYPE_DSI>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; status = "disabled"; @@ -1816,7 +1884,7 @@ dsi1: dsi@fde30000 { resets = <&cru SRST_P_DSIHOST1>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipidcphy1 PHY_TYPE_DPHY>; + phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_TYPE_DSI>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; status = "disabled"; @@ -3429,7 +3497,7 @@ mipidcphy0: phy@feda0000 { <&cru SRST_P_MIPI_DCPHY0_GRF>, <&cru SRST_S_MIPI_DCPHY0>; reset-names = "m_phy", "apb", "grf", "s_phy"; - #phy-cells = <1>; + #phy-cells = <2>; status = "disabled"; }; @@ -3445,7 +3513,7 @@ mipidcphy1: phy@fedb0000 { <&cru SRST_P_MIPI_DCPHY1_GRF>, <&cru SRST_S_MIPI_DCPHY1>; reset-names = "m_phy", "apb", "grf", "s_phy"; - #phy-cells = <1>; + #phy-cells = <2>; status = "disabled"; }; -- 2.43.0 -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97434C624DE for ; Fri, 4 Sep 2026 07:56:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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[211.23.39.77]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c397b1sm9356695a91.8.2026.09.04.00.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 00:56:36 -0700 (PDT) From: Jason Yang To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: Michael Riesch , Sebastian Reichel , Bryan O'Donoghue , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang Subject: [RFC PATCH] arm64: dts: rockchip: add mipi csi-2 receiver nodes for the dcphys on rk3588 Date: Fri, 4 Sep 2026 15:55:34 +0800 Message-ID: <20260904075534.574037-1-jason98166@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <8e10a8c0-3648-47b5-9131-a1abdd7eb8c5@kernel.org> References: <8e10a8c0-3648-47b5-9131-a1abdd7eb8c5@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260904_005639_130675_33CE4347 X-CRM114-Status: GOOD ( 13.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is test patch, contains the following 3 changes: - raise #phy-cells to 2 - add PHY_TYPE_DSI to the dsi nodes - add mipi csi0 and csi1 Signed-off-by: Jason Yang --- Hi Michael, Krzysztof, Here is the test patch for https://lore.kernel.org/r/20260821-dcphy-rx-v1-v4-0-f1797634233d@gmail.com I have tested imx219/ov5640 stream with csi0 and meanwhile stream on rpi panel with dsi0, both using mipidcphy0. Related commits: 2e177b85541d ("arm64: dts: rockchip: add mipi dcphy nodes to rk3588") 0d0947766d87 ("arm64: dts: rockchip: add dsi controller nodes on rk3588") 5052c99cf052 ("arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588") Best regards, Jason arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 76 ++++++++++++++++++- 1 file changed, 72 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index fc1fdbfd3162..dd2bbc02f8d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1516,10 +1516,18 @@ vicap_dvp: port@0 { vicap_mipi0: port@1 { reg = <0x1>; + + vicap_mipi0_input: endpoint { + remote-endpoint = <&csi0_output>; + }; }; vicap_mipi1: port@2 { reg = <0x2>; + + vicap_mipi1_input: endpoint { + remote-endpoint = <&csi1_output>; + }; }; vicap_mipi2: port@3 { @@ -1568,6 +1576,66 @@ vicap_mmu: iommu@fdce0800 { status = "disabled"; }; + csi0: csi@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd10000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_0>; + phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_TYPE_CSI>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_in: port@0 { + reg = <0>; + }; + + csi0_out: port@1 { + reg = <1>; + + csi0_output: endpoint { + remote-endpoint = <&vicap_mipi0_input>; + }; + }; + }; + }; + + csi1: csi@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd20000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_1>; + phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_TYPE_CSI>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_in: port@0 { + reg = <0>; + }; + + csi1_out: port@1 { + reg = <1>; + + csi1_output: endpoint { + remote-endpoint = <&vicap_mipi1_input>; + }; + }; + }; + }; + csi2: csi@fdd30000 { compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdd30000 0x0 0x10000>; @@ -1788,7 +1856,7 @@ dsi0: dsi@fde20000 { resets = <&cru SRST_P_DSIHOST0>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipidcphy0 PHY_TYPE_DPHY>; + phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_TYPE_DSI>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; status = "disabled"; @@ -1816,7 +1884,7 @@ dsi1: dsi@fde30000 { resets = <&cru SRST_P_DSIHOST1>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipidcphy1 PHY_TYPE_DPHY>; + phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_TYPE_DSI>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; status = "disabled"; @@ -3429,7 +3497,7 @@ mipidcphy0: phy@feda0000 { <&cru SRST_P_MIPI_DCPHY0_GRF>, <&cru SRST_S_MIPI_DCPHY0>; reset-names = "m_phy", "apb", "grf", "s_phy"; - #phy-cells = <1>; + #phy-cells = <2>; status = "disabled"; }; @@ -3445,7 +3513,7 @@ mipidcphy1: phy@fedb0000 { <&cru SRST_P_MIPI_DCPHY1_GRF>, <&cru SRST_S_MIPI_DCPHY1>; reset-names = "m_phy", "apb", "grf", "s_phy"; - #phy-cells = <1>; + #phy-cells = <2>; status = "disabled"; }; -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C269C79F85 for ; Fri, 4 Sep 2026 07:56:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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[211.23.39.77]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08c397b1sm9356695a91.8.2026.09.04.00.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 00:56:36 -0700 (PDT) From: Jason Yang To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: Michael Riesch , Sebastian Reichel , Bryan O'Donoghue , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang Subject: [RFC PATCH] arm64: dts: rockchip: add mipi csi-2 receiver nodes for the dcphys on rk3588 Date: Fri, 4 Sep 2026 15:55:34 +0800 Message-ID: <20260904075534.574037-1-jason98166@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <8e10a8c0-3648-47b5-9131-a1abdd7eb8c5@kernel.org> References: <8e10a8c0-3648-47b5-9131-a1abdd7eb8c5@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260904_005639_124806_28FEEC9A X-CRM114-Status: GOOD ( 11.97 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org This is test patch, contains the following 3 changes: - raise #phy-cells to 2 - add PHY_TYPE_DSI to the dsi nodes - add mipi csi0 and csi1 Signed-off-by: Jason Yang --- Hi Michael, Krzysztof, Here is the test patch for https://lore.kernel.org/r/20260821-dcphy-rx-v1-v4-0-f1797634233d@gmail.com I have tested imx219/ov5640 stream with csi0 and meanwhile stream on rpi panel with dsi0, both using mipidcphy0. Related commits: 2e177b85541d ("arm64: dts: rockchip: add mipi dcphy nodes to rk3588") 0d0947766d87 ("arm64: dts: rockchip: add dsi controller nodes on rk3588") 5052c99cf052 ("arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588") Best regards, Jason arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 76 ++++++++++++++++++- 1 file changed, 72 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index fc1fdbfd3162..dd2bbc02f8d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1516,10 +1516,18 @@ vicap_dvp: port@0 { vicap_mipi0: port@1 { reg = <0x1>; + + vicap_mipi0_input: endpoint { + remote-endpoint = <&csi0_output>; + }; }; vicap_mipi1: port@2 { reg = <0x2>; + + vicap_mipi1_input: endpoint { + remote-endpoint = <&csi1_output>; + }; }; vicap_mipi2: port@3 { @@ -1568,6 +1576,66 @@ vicap_mmu: iommu@fdce0800 { status = "disabled"; }; + csi0: csi@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd10000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_0>; + phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_TYPE_CSI>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_in: port@0 { + reg = <0>; + }; + + csi0_out: port@1 { + reg = <1>; + + csi0_output: endpoint { + remote-endpoint = <&vicap_mipi0_input>; + }; + }; + }; + }; + + csi1: csi@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; + reg = <0x0 0xfdd20000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "err1", "err2"; + clocks = <&cru PCLK_CSI_HOST_1>; + phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_TYPE_CSI>; + power-domains = <&power RK3588_PD_VI>; + resets = <&cru SRST_P_CSI_HOST_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_in: port@0 { + reg = <0>; + }; + + csi1_out: port@1 { + reg = <1>; + + csi1_output: endpoint { + remote-endpoint = <&vicap_mipi1_input>; + }; + }; + }; + }; + csi2: csi@fdd30000 { compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2"; reg = <0x0 0xfdd30000 0x0 0x10000>; @@ -1788,7 +1856,7 @@ dsi0: dsi@fde20000 { resets = <&cru SRST_P_DSIHOST0>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipidcphy0 PHY_TYPE_DPHY>; + phys = <&mipidcphy0 PHY_TYPE_DPHY PHY_TYPE_DSI>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; status = "disabled"; @@ -1816,7 +1884,7 @@ dsi1: dsi@fde30000 { resets = <&cru SRST_P_DSIHOST1>; reset-names = "apb"; power-domains = <&power RK3588_PD_VOP>; - phys = <&mipidcphy1 PHY_TYPE_DPHY>; + phys = <&mipidcphy1 PHY_TYPE_DPHY PHY_TYPE_DSI>; phy-names = "dcphy"; rockchip,grf = <&vop_grf>; status = "disabled"; @@ -3429,7 +3497,7 @@ mipidcphy0: phy@feda0000 { <&cru SRST_P_MIPI_DCPHY0_GRF>, <&cru SRST_S_MIPI_DCPHY0>; reset-names = "m_phy", "apb", "grf", "s_phy"; - #phy-cells = <1>; + #phy-cells = <2>; status = "disabled"; }; @@ -3445,7 +3513,7 @@ mipidcphy1: phy@fedb0000 { <&cru SRST_P_MIPI_DCPHY1_GRF>, <&cru SRST_S_MIPI_DCPHY1>; reset-names = "m_phy", "apb", "grf", "s_phy"; - #phy-cells = <1>; + #phy-cells = <2>; status = "disabled"; }; -- 2.43.0 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip