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Fri, 04 Sep 2026 04:17:42 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, johan.almbladh@anyfinetworks.com, paulburton@kernel.org, tsbogend@alpha.franken.de Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, bpf@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH bpf-next v2 0/2] bpf, mips: Add BPF_MOVSX support to the JITs Date: Fri, 4 Sep 2026 07:17:29 -0400 Message-ID: <20260904111731.673341-1-main.kalliope@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MIPS32 and MIPS64 JITs lower register BPF_MOVSX as an ordinary MOV because their move paths ignore insn->off. The instruction is therefore silently miscompiled instead of falling back to the interpreter. Patch 1 factors ALU32 and ALU64 register moves into backend-local helpers. Patch 2 decodes the MOVSX width from insn->off in those helpers, keeping MIPS32 register-pair handling and the existing ALU32 upper-half paths inside the move operation. This is missing architecture support rather than a regression. Core MOVSX support arrived after both backends, and the analogous RV32 change (c6a08afdfe3a, "riscv, bpf: Add support for BPF_MOVSX in RV32 JIT") went through bpf-next without a Fixes tag. This series can be applied before or after the in-flight SDIV/SMOD series. Both are semantic prerequisites for MEMSX. The ordering discussion is here: Link: https://lore.kernel.org/bpf/CAJZwKkis=3NGw9At0WfiZaRYEoMPbQfqJKN0e+vtRDvp4VY5Ng@mail.gmail.com/ Targeted MOVSX and MOV control testing under QEMU Malta covered MIPS32 R1, R2, and R6 and MIPS64 R2 in both endian configurations, plus MIPS64 R6 little endian. All 180 runs required the JIT and covered the baseline, helper-only, and final series boundaries. I also ran the complete unfiltered lib/test_bpf.c suite directly on the final v2 candidate with CONFIG_BPF_JIT_ALWAYS_ON=y on little-endian MIPS32 R2 and R6 and MIPS64 R2 and R6. The MIPS32 profiles returned 1036 passes and 26 failures; the MIPS64 profiles returned 1035 passes and 26 failures. All five MOVSX cases passed on every profile. The 26 remaining failures were 14 SDIV/SMOD, 8 BSWAP, 3 MEMSX, and 1 JMP32_JA case. Existing lib/test_bpf.c cases exercise all five valid MOVSX forms on MIPS, while verifier_movsx.c covers the generic verifier contract. No physical MIPS hardware was tested. Changes requested by Johan Almbladh in review of RFC v1: - Group the 8- and 16-bit cases and compute the shift from insn->off. - Move clobber bookkeeping to common emitter tails. - Avoid early returns and use emit_sext() for MIPS64 MOVSX32. Other changes in v2: - Document why width decoding belongs in the move helpers, the supported ISA floor, and why other MOV offsets cannot reach these paths. - Run the complete test_bpf suite directly on v2 on four little-endian ISA profiles. v1: https://lore.kernel.org/bpf/20260819010523.1057789-1-main.kalliope@gmail.com/ Nicholas Dudar (2): bpf, mips: Factor register moves into helpers bpf, mips: Add support for BPF_MOVSX in the JITs arch/mips/net/bpf_jit_comp32.c | 60 +++++++++++++++++++++++++++++++--- arch/mips/net/bpf_jit_comp64.c | 56 +++++++++++++++++++++++++++++-- 2 files changed, 109 insertions(+), 7 deletions(-) base-commit: 6655c409707ec8ce9ce0850ffe4fe02331fd4d9c