From: Hemanth Selam <hemanth.selam@gmail.com>
To: Herbert Xu <herbert@gondor.apana.org.au>,
"David S. Miller" <davem@davemloft.net>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Alexandre Belloni <alexandre.belloni@bootlin.com>,
Claudiu Beznea <claudiu.beznea@tuxon.dev>,
George Cherian <gcherian@marvell.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
John Allen <john.allen@amd.com>,
Gilad Ben-Yossef <gilad@benyossef.com>,
Ayush Sawal <ayush.sawal@chelsio.com>,
Srujana Challa <schalla@marvell.com>,
Bharat Bhushan <bbhushan2@marvell.com>,
Bartosz Golaszewski <brgl@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Vladimir Zapolskiy <vz@mleia.com>
Cc: linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Subject: [PATCH] crypto: fix typos in comments
Date: Fri, 4 Sep 2026 17:13:39 +0530 [thread overview]
Message-ID: <20260904114345.27509-1-hemanth.selam@gmail.com> (raw)
Fix typos in comments, reported by scripts/checkpatch.pl using the
misspelling list in scripts/spelling.txt. Only touches comments, no code
changes.
Assisted-by: Cursor:claude-opus-5
Signed-off-by: Hemanth Selam <hemanth.selam@gmail.com>
---
drivers/crypto/atmel-sha.c | 4 ++--
drivers/crypto/cavium/cpt/cptpf_main.c | 12 ++++++------
drivers/crypto/cavium/cpt/cptvf_main.c | 4 ++--
drivers/crypto/cavium/cpt/cptvf_mbox.c | 4 ++--
drivers/crypto/cavium/nitrox/nitrox_main.c | 2 +-
drivers/crypto/ccp/ccp-dev.c | 2 +-
drivers/crypto/ccree/cc_buffer_mgr.c | 4 ++--
drivers/crypto/chelsio/chcr_algo.c | 2 +-
drivers/crypto/hisilicon/sec/sec_algs.c | 2 +-
drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c | 4 ++--
drivers/crypto/omap-sham.c | 4 ++--
drivers/crypto/qce/aead.c | 2 +-
drivers/crypto/s5p-sss.c | 2 +-
13 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/crypto/atmel-sha.c b/drivers/crypto/atmel-sha.c
index 48f54b615504..89c0a3bdf4e0 100644
--- a/drivers/crypto/atmel-sha.c
+++ b/drivers/crypto/atmel-sha.c
@@ -1203,7 +1203,7 @@ static int atmel_sha_finup(struct ahash_request *req)
/*
* final() has to be always called to cleanup resources
- * even if udpate() failed, except EINPROGRESS
+ * even if update() failed, except EINPROGRESS
*/
err2 = atmel_sha_final(req);
@@ -1338,7 +1338,7 @@ static int atmel_sha_done(struct atmel_sha_dev *dd)
return err;
finish:
- /* finish curent request */
+ /* finish current request */
atmel_sha_finish_req(dd->req, err);
return err;
diff --git a/drivers/crypto/cavium/cpt/cptpf_main.c b/drivers/crypto/cavium/cpt/cptpf_main.c
index 9358c1c041d4..4234f9f156a3 100644
--- a/drivers/crypto/cavium/cpt/cptpf_main.c
+++ b/drivers/crypto/cavium/cpt/cptpf_main.c
@@ -90,19 +90,19 @@ static void cpt_configure_group(struct cpt_device *cpt, u8 grp,
static void cpt_disable_mbox_interrupts(struct cpt_device *cpt)
{
- /* Clear mbox(0) interupts for all vfs */
+ /* Clear mbox(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull);
}
static void cpt_disable_ecc_interrupts(struct cpt_device *cpt)
{
- /* Clear ecc(0) interupts for all vfs */
+ /* Clear ecc(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull);
}
static void cpt_disable_exec_interrupts(struct cpt_device *cpt)
{
- /* Clear exec interupts for all vfs */
+ /* Clear exec interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull);
}
@@ -115,7 +115,7 @@ static void cpt_disable_all_interrupts(struct cpt_device *cpt)
static void cpt_enable_mbox_interrupts(struct cpt_device *cpt)
{
- /* Set mbox(0) interupts for all vfs */
+ /* Set mbox(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull);
}
@@ -140,10 +140,10 @@ static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
*/
if (mcode->is_ae) {
core = CPT_MAX_SE_CORES; /* start couting from 10 */
- total_cores = CPT_MAX_TOTAL_CORES; /* upto 15 */
+ total_cores = CPT_MAX_TOTAL_CORES; /* up to 15 */
} else {
core = 0; /* start couting from 0 */
- total_cores = CPT_MAX_SE_CORES; /* upto 9 */
+ total_cores = CPT_MAX_SE_CORES; /* up to 9 */
}
/* Point to microcode for each core of the group */
diff --git a/drivers/crypto/cavium/cpt/cptvf_main.c b/drivers/crypto/cavium/cpt/cptvf_main.c
index db76df14c4a0..e07448098ac0 100644
--- a/drivers/crypto/cavium/cpt/cptvf_main.c
+++ b/drivers/crypto/cavium/cpt/cptvf_main.c
@@ -417,7 +417,7 @@ static void cptvf_enable_swerr_interrupts(struct cpt_vf *cptvf)
vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,
CPTX_VQX_MISC_ENA_W1S(0, 0));
- /* Set mbox(0) interupts for the requested vf */
+ /* Set mbox(0) interrupts for the requested vf */
vqx_misc_ena.s.swerr = 1;
cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),
vqx_misc_ena.u);
@@ -429,7 +429,7 @@ static void cptvf_enable_mbox_interrupts(struct cpt_vf *cptvf)
vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,
CPTX_VQX_MISC_ENA_W1S(0, 0));
- /* Set mbox(0) interupts for the requested vf */
+ /* Set mbox(0) interrupts for the requested vf */
vqx_misc_ena.s.mbox = 1;
cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),
vqx_misc_ena.u);
diff --git a/drivers/crypto/cavium/cpt/cptvf_mbox.c b/drivers/crypto/cavium/cpt/cptvf_mbox.c
index 1267e1eba7e9..9f2ae10bbd60 100644
--- a/drivers/crypto/cavium/cpt/cptvf_mbox.c
+++ b/drivers/crypto/cavium/cpt/cptvf_mbox.c
@@ -120,7 +120,7 @@ int cptvf_send_vq_size_msg(struct cpt_vf *cptvf)
}
/*
- * Communicate VF group required to PF and get the VQ binded to that group
+ * Communicate VF group required to PF and get the VQ bound to that group
*/
int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf)
{
@@ -139,7 +139,7 @@ int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf)
}
/*
- * Communicate VF group required to PF and get the VQ binded to that group
+ * Communicate VF group required to PF and get the VQ bound to that group
*/
int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf)
{
diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c
index e474c84d8d38..54b2db6bb5d0 100644
--- a/drivers/crypto/cavium/nitrox/nitrox_main.c
+++ b/drivers/crypto/cavium/nitrox/nitrox_main.c
@@ -468,7 +468,7 @@ static int nitrox_probe(struct pci_dev *pdev,
err = -EIO;
goto ioremap_err;
}
- /* allocate command queus based on cpus, max queues are 64 */
+ /* allocate command queues based on cpus, max queues are 64 */
ndev->nr_queues = min_t(u32, MAX_PF_QUEUES, num_online_cpus());
ndev->qlen = qlen;
diff --git a/drivers/crypto/ccp/ccp-dev.c b/drivers/crypto/ccp/ccp-dev.c
index 246801912e1a..aff3348b8351 100644
--- a/drivers/crypto/ccp/ccp-dev.c
+++ b/drivers/crypto/ccp/ccp-dev.c
@@ -30,7 +30,7 @@
#define MAX_CCPS 32
-/* Limit CCP use to a specifed number of queues per device */
+/* Limit CCP use to a specified number of queues per device */
static unsigned int nqueues;
module_param(nqueues, uint, 0444);
MODULE_PARM_DESC(nqueues, "Number of queues per CCP (minimum 1; default: all available)");
diff --git a/drivers/crypto/ccree/cc_buffer_mgr.c b/drivers/crypto/ccree/cc_buffer_mgr.c
index dc7e0cd51c25..a592f5ec1b6a 100644
--- a/drivers/crypto/ccree/cc_buffer_mgr.c
+++ b/drivers/crypto/ccree/cc_buffer_mgr.c
@@ -717,7 +717,7 @@ static void cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata,
}
} else { /* Contig. ICV */
sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
- /*Should hanlde if the sg is not contig.*/
+ /*Should handle if the sg is not contig.*/
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
(*src_last_bytes - authsize);
areq_ctx->icv_virt_addr = sg_virt(sg) +
@@ -749,7 +749,7 @@ static void cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata,
} else { /* Contig. ICV */
sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
- /*Should hanlde if the sg is not contig.*/
+ /*Should handle if the sg is not contig.*/
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
(*src_last_bytes - authsize);
areq_ctx->icv_virt_addr = sg_virt(sg) +
diff --git a/drivers/crypto/chelsio/chcr_algo.c b/drivers/crypto/chelsio/chcr_algo.c
index 6dec42282768..e2f2b2a6200e 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -1605,7 +1605,7 @@ static struct sk_buff *create_hash_wr(struct ahash_request *req,
req_ctx->hctx_wr.dma_addr = 0;
}
chcr_add_hash_src_ent(req, ulptx, param);
- /* Request upto max wr size */
+ /* Request up to max wr size */
temp = param->kctx_len + DUMMY_BYTES + (req_ctx->hctx_wr.imm ?
(param->sg_len + param->bfr_len) : 0);
atomic_inc(&adap->chcr_stats.digest_rqst);
diff --git a/drivers/crypto/hisilicon/sec/sec_algs.c b/drivers/crypto/hisilicon/sec/sec_algs.c
index 85eecbb40e7e..995aa598a1ed 100644
--- a/drivers/crypto/hisilicon/sec/sec_algs.c
+++ b/drivers/crypto/hisilicon/sec/sec_algs.c
@@ -790,7 +790,7 @@ static int sec_alg_skcipher_crypto(struct skcipher_request *skreq,
/*
* Only attempt to queue if the whole lot can fit in the queue -
- * we can't successfully cleanup after a partial queing so this
+ * we can't successfully cleanup after a partial queuing so this
* must succeed or fail atomically.
*
* Big hammer test of both software and hardware queues - could be
diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c b/drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c
index 90fdafb7c468..38d1de24652b 100644
--- a/drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c
+++ b/drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c
@@ -180,7 +180,7 @@ int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf)
}
/*
- * Communicate VF group required to PF and get the VQ binded to that group
+ * Communicate VF group required to PF and get the VQ bound to that group
*/
int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group)
{
@@ -199,7 +199,7 @@ int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group)
}
/*
- * Communicate VF group required to PF and get the VQ binded to that group
+ * Communicate VF group required to PF and get the VQ bound to that group
*/
int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf)
{
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index 6d2dd0b88f15..12d6dc68438a 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -1265,7 +1265,7 @@ static int omap_sham_finup(struct ahash_request *req)
return err1;
/*
* final() has to be always called to cleanup resources
- * even if udpate() failed, except EINPROGRESS
+ * even if update() failed, except EINPROGRESS
*/
err2 = omap_sham_final(req);
@@ -1732,7 +1732,7 @@ static void omap_sham_done_task(struct work_struct *t)
finish:
dev_dbg(dd->dev, "update done: err: %d\n", err);
- /* finish curent request */
+ /* finish current request */
omap_sham_finish_req(dd->req, err);
}
diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c
index a9642c67f476..a6b446bbb499 100644
--- a/drivers/crypto/qce/aead.c
+++ b/drivers/crypto/qce/aead.c
@@ -379,7 +379,7 @@ static int qce_aead_create_ccm_nonce(struct qce_aead_reqctx *rctx, struct qce_ae
/*
* The crypto framework encodes cryptlen as unsigned int. Thus, even though
- * spec allows for upto 8 bytes to encode msg_len only 4 bytes are needed.
+ * spec allows for up to 8 bytes to encode msg_len only 4 bytes are needed.
*/
if (msglen_size > 4)
msglen_size = 4;
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index bdda7b39af85..60547fa89ac4 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -1446,7 +1446,7 @@ static void s5p_hash_tasklet_cb(unsigned long data)
return;
finish:
- /* finish curent request */
+ /* finish current request */
s5p_hash_finish_req(dd->hash_req, 0);
/* If we are not busy, process next req */
--
2.48.1
next reply other threads:[~2026-09-04 11:43 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 11:43 Hemanth Selam [this message]
2026-09-07 12:35 ` [PATCH] crypto: fix typos in comments Thomas Huth
2026-09-07 13:43 ` Bartosz Golaszewski
2026-09-16 12:53 ` Herbert Xu
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