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envelope-from=bin.meng@processmission.com; helo=TYDPR03CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org The generic OpenSBI platform derives the CLINT first hart and register slot count from interrupts-extended. Some S-mode-only MPFS device trees mask the E51 M-mode interrupt entries with 0xffffffff, which shifts the MSIP and MTIMECMP slots when the same DTB is used for direct boot. Document the complete five-hart CLINT node. Require interrupts 3 and 7 for hart 0 as well as the U54 harts. Signed-off-by: Bin Meng --- (no changes since v1) docs/system/riscv/microchip-icicle-kit.rst | 23 +++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst index eeb4ff938c..af8e984df7 100644 --- a/docs/system/riscv/microchip-icicle-kit.rst +++ b/docs/system/riscv/microchip-icicle-kit.rst @@ -65,7 +65,28 @@ should meet the following requirements: option. * It should contain a node for the CLINT device with a compatible string - "riscv,clint0". + "riscv,clint0" or "sifive,clint0". Its ``interrupts-extended`` property + must describe the M-mode software interrupt (3) and timer interrupt (7) for + every hart, including the E51 hart 0. + +For example, the five-hart Icicle Kit CLINT node can be described as: + +.. code-block:: none + + clint: clint@2000000 { + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0xc000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + +Do not replace the hart 0 interrupt numbers with ``0xffffffff`` when the same +DTB is used to initialize the generic OpenSBI platform. OpenSBI derives the +first hart and the number of CLINT register slots from these interrupt tuples; +masking hart 0 would shift the per-hart MSIP and MTIMECMP register mappings. When ``-bios`` is not specified or set to ``default``, the OpenSBI ``fw_dynamic`` BIOS image for the ``generic`` platform is used to boot an -- 2.53.0