Re: [PATCH v2 1/4] hw/pci: add IDE + TEE capability to PCIe root port

["Michael S. Tsirkin" <mst@redhat.com>]

On Fri, Sep 04, 2026 at 05:05:01PM +0100, Jim MacArthur wrote:
> From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> 

Please include a commit log explaining the motivation,
alternatives and result.

A possible format:

Currently .... as a result .... we can not .... because ....
To fix ... and then ...




> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
> ---
>  hw/pci-bridge/gen_pcie_root_port.c |  8 ++++++++
>  hw/pci/pcie.c                      | 15 +++++++++++++++
>  include/hw/pci/pcie.h              |  3 +++
>  include/hw/pci/pcie_regs.h         |  4 ++++
>  4 files changed, 30 insertions(+)
> 
> diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c
> index 5434d693d9..452ebf69b3 100644
> --- a/hw/pci-bridge/gen_pcie_root_port.c
> +++ b/hw/pci-bridge/gen_pcie_root_port.c
> @@ -26,6 +26,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, GEN_PCIE_ROOT_PORT)
>  #define GEN_PCIE_ROOT_PORT_AER_OFFSET           0x100
>  #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
>          (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
> +#define GEN_PCIE_ROOT_PORT_ACS_END \
> +        (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF)
>  
>  #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR       1
>  #define GEN_PCIE_ROOT_DEFAULT_IO_RANGE          4096
> @@ -100,6 +102,12 @@ static void gen_rp_realize(DeviceState *dev, Error **errp)
>          d->wmask[PCI_IO_BASE] = 0;
>          d->wmask[PCI_IO_LIMIT] = 0;
>      }
> +
> +    uint32_t offset = GEN_PCIE_ROOT_PORT_ACS_END;
> +    pcie_ide_init(d, offset);
> +    offset += PCI_IDE_SIZEOF;
> +
> +    pcie_cap_tee_init(d);
>  }
>  
>  static const VMStateDescription vmstate_rp_dev = {
> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> index 4622c75e48..b9ead826ed 100644
> --- a/hw/pci/pcie.c
> +++ b/hw/pci/pcie.c
> @@ -968,6 +968,12 @@ void pcie_cap_flr_write_config(PCIDevice *dev,
>      }
>  }
>  
> +void pcie_cap_tee_init(PCIDevice *dev)
> +{
> +    pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
> +                               PCI_EXP_DEVCAP_TEE);
> +}
> +
>  /* Alternative Routing-ID Interpretation (ARI)
>   * forwarding support for root and downstream ports
>   */
> @@ -1371,6 +1377,15 @@ uint32_t pcie_pri_get_req_alloc(const PCIDevice *dev)
>      return pci_get_long(dev->config + dev->exp.pri_cap + PCI_PRI_ALLOC_REQ);
>  }
>  
> +/* IDE */
> +void pcie_ide_init(PCIDevice *dev, uint16_t offset)
> +{
> +    pcie_add_capability(dev, PCI_EXT_CAP_ID_IDE, PCI_IDE_VER,
> +                        offset, PCI_IDE_SIZEOF);
> +    uint32_t cap = PCI_IDE_CAP_SELECTIVE;
> +    pci_set_byte(dev->config + offset + PCI_IDE_CAP, cap);
> +}
> +
>  bool pcie_pri_enabled(const PCIDevice *dev)
>  {
>      if (!pci_is_express(dev) || !dev->exp.pri_cap) {
> diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
> index 71ba94874b..db66678252 100644
> --- a/include/hw/pci/pcie.h
> +++ b/include/hw/pci/pcie.h
> @@ -123,6 +123,8 @@ void pcie_cap_flr_init(PCIDevice *dev);
>  void pcie_cap_flr_write_config(PCIDevice *dev,
>                             uint32_t addr, uint32_t val, int len);
>  
> +void pcie_cap_tee_init(PCIDevice *dev);
> +
>  /* ARI forwarding capability and control */
>  void pcie_cap_arifwd_init(PCIDevice *dev);
>  void pcie_cap_arifwd_reset(PCIDevice *dev);
> @@ -161,6 +163,7 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
>                       bool exec_perm, bool priv_mod);
>  void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_pr_cap,
>                     bool prg_response_pasid_req);
> +void pcie_ide_init(PCIDevice *dev, uint16_t offset);
>  
>  uint32_t pcie_pri_get_req_alloc(const PCIDevice *dev);
>  bool pcie_pri_enabled(const PCIDevice *dev);
> diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h
> index 33a22229fe..aa21177411 100644
> --- a/include/hw/pci/pcie_regs.h
> +++ b/include/hw/pci/pcie_regs.h
> @@ -182,4 +182,8 @@ typedef enum PCIExpLinkWidth {
>  #define PCI_DOE_VER                     0x1
>  #define PCI_DOE_SIZEOF                  24
>  
> +/* IDE */
> +#define PCI_IDE_VER                     0x1
> +#define PCI_IDE_SIZEOF                  12
> +
>  #endif /* QEMU_PCIE_REGS_H */
> 
> -- 
> 2.43.0