From: Xiaogang.Chen <xiaogang.chen@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Xiaogang Chen <xiaogang.chen@amd.com>
Subject: [PATCH v2 4/4] drm/amdkfd: Apply AMDGPU_PTE_FRAG to pte of gart page table for THP mapping
Date: Fri, 4 Sep 2026 14:54:21 -0500 [thread overview]
Message-ID: <20260904195421.42919-5-xiaogang.chen@amd.com> (raw)
In-Reply-To: <20260904195421.42919-1-xiaogang.chen@amd.com>
From: Xiaogang Chen <xiaogang.chen@amd.com>
When both sys ram and vram are physical continuous HPAGE_PMD_NR pages during
migration set AMDGPU_PTE_FRAG(HPAGE_PMD_ORDER) at pte in gart page table to
let hardware know the migrating pages are HPAGE_PMD_NR size THP. That will
reduce hardware TLB pressure or increase TLB hit ration.
Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 45 ++++++++++++++----------
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index af39e547c1fa..8a2fbe3a7613 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -48,7 +48,7 @@ static int
svm_migrate_gart_map(struct amdgpu_ring *ring,
struct amdgpu_ttm_buffer_entity *entity,
u64 npages,
- dma_addr_t *addr, u64 *gart_addr, u64 flags)
+ dma_addr_t *addr, u64 *gart_addr, u64 flags, bool is_thp)
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_job *job;
@@ -90,6 +90,9 @@ svm_migrate_gart_map(struct amdgpu_ring *ring,
pte_flags |= AMDGPU_PTE_WRITEABLE;
pte_flags |= adev->gart.gart_pte_flags;
+ if (is_thp)
+ pte_flags |= AMDGPU_PTE_FRAG(HPAGE_PMD_ORDER);
+
cpu_addr = &job->ibs[0].ptr[num_dw];
amdgpu_gart_map(adev, 0, npages, addr, pte_flags, cpu_addr);
@@ -108,6 +111,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring,
* @npages: number of pages to copy
* @direction: enum MIGRATION_COPY_DIR
* @mfence: output, sdma fence to signal after sdma is done
+ * @is_thp: both sys and vram are physical continuous HPAGE_PMD_NR pages
*
* ram address uses GART table continuous entries mapping to ram pages,
* vram address uses direct mapping of vram pages, which must have npages
@@ -126,7 +130,7 @@ static int
svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
u64 *vram, u64 npages,
enum MIGRATION_COPY_DIR direction,
- struct dma_fence **mfence)
+ struct dma_fence **mfence, bool is_thp)
{
const u64 GTT_MAX_PAGES = (AMDGPU_GTT_MAX_TRANSFER_SIZE >> PAGE_SHIFT);
struct amdgpu_ring *ring;
@@ -136,6 +140,12 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
u64 size;
int r = 0;
+ if (is_thp && npages != HPAGE_PMD_NR) {
+ dev_warn(adev->dev, "THP migration should have %d pages\n",
+ HPAGE_PMD_NR);
+ is_thp = false;
+ }
+
ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]);
entity = &adev->mman.move_entities[0];
@@ -146,11 +156,12 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
if (direction == FROM_VRAM_TO_RAM) {
gart_s = svm_migrate_direct_mapping_addr(adev, *vram);
- r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0);
+ r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0,
+ is_thp);
} else if (direction == FROM_RAM_TO_VRAM) {
r = svm_migrate_gart_map(ring, entity, size, sys, &gart_s,
- KFD_IOCTL_SVM_FLAG_GPU_RO);
+ KFD_IOCTL_SVM_FLAG_GPU_RO, is_thp);
gart_d = svm_migrate_direct_mapping_addr(adev, *vram);
}
if (r) {
@@ -362,7 +373,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange,
adev, src + i - j,
dst + i - j, j,
FROM_RAM_TO_VRAM,
- mfence);
+ mfence, false);
if (r)
goto out_free_vram_pages;
@@ -398,7 +409,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange,
adev, src + i,
dst + i, HPAGE_PMD_NR,
FROM_RAM_TO_VRAM,
- mfence);
+ mfence, true);
/* mark head page dma mapping as THP, tail pages dma addr
* are set to 0 for following dma_unmap
@@ -433,7 +444,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange,
adev, src + i - j,
dst + i - j, j,
FROM_RAM_TO_VRAM,
- mfence);
+ mfence, false);
if (r)
goto out_free_vram_pages;
@@ -452,7 +463,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange,
r = svm_migrate_copy_memory_gart(adev, src + i - j,
dst + i - j, j,
FROM_RAM_TO_VRAM,
- mfence);
+ mfence, false);
if (r)
goto out_free_vram_pages;
}
@@ -466,7 +477,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange,
if (j > 0)
r = svm_migrate_copy_memory_gart(adev, src + i - j, dst + i - j, j,
- FROM_RAM_TO_VRAM, mfence);
+ FROM_RAM_TO_VRAM, mfence, false);
out_free_vram_pages:
if (r) {
@@ -736,7 +747,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
r = svm_migrate_copy_memory_gart(adev, dst + i - j,
src + i - j, j,
FROM_VRAM_TO_RAM,
- mfence);
+ mfence, false);
if (r)
goto out_oom;
j = 0;
@@ -751,7 +762,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
r = svm_migrate_copy_memory_gart(adev, dst + i - j,
src + i - j, j,
FROM_VRAM_TO_RAM,
- mfence);
+ mfence, false);
if (r)
goto out_oom;
j = 0;
@@ -795,7 +806,8 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
/* migrate previous accumulated pages */
if(j) {
r = svm_migrate_copy_memory_gart(adev, dst + i - j,
- src + i - j, j, FROM_VRAM_TO_RAM, mfence);
+ src + i - j, j, FROM_VRAM_TO_RAM,
+ mfence, false);
if (r)
goto out_oom;
j = 0;
@@ -809,14 +821,11 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
}
/* migrate the HPAGE_PMD_NR pages above */
- /* svm_migrate_copy_memory_gart will add a paramter to indicate
- * the migration is for 2MB THP
- */
r = svm_migrate_copy_memory_gart(
adev, dst + i,
src + i, HPAGE_PMD_NR,
FROM_VRAM_TO_RAM,
- mfence);
+ mfence, true);
/* mark head page dma mapping as THP, tail pages dma addr
* are set to 0 for following dma_unmap
@@ -837,7 +846,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange,
if (j > 0)
r = svm_migrate_copy_memory_gart(adev, dst + i - j, src + i - j, j,
- FROM_VRAM_TO_RAM, mfence);
+ FROM_VRAM_TO_RAM, mfence, false);
out_oom:
if (r) {
pr_debug("failed %d copy to ram\n", r);
@@ -1299,7 +1308,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
amdgpu_amdkfd_reserve_system_mem(SVM_HMM_PAGE_STRUCT_SIZE(size));
- pr_info("---XCHEN 3.2 HMM registered %ldMB device memory\n", size >> 20);
+ pr_info("HMM registered %ldMB device memory\n", size >> 20);
return 0;
}
--
2.34.1
prev parent reply other threads:[~2026-09-04 19:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 19:54 [PATCH v2 0/4] drm/amdkfd: Enable device private memory THP support in kfd svm driver Xiaogang.Chen
2026-09-04 19:54 ` [PATCH v2 1/4] drm/amdkfd: Add awareness of THP of device and system RAM " Xiaogang.Chen
2026-09-04 19:54 ` [PATCH v2 2/4] drm/amdkfd: Change migration size in CPU/GPU page fault handler to THP size Xiaogang.Chen
2026-09-04 19:54 ` [PATCH v2 3/4] drm/amdkfd: Apply HMM THP zone device-private memory migration in kfd driver Xiaogang.Chen
2026-09-04 19:54 ` Xiaogang.Chen [this message]
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