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envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org The harts requirements of RISC-V server platform [1] require RVA23 ISA profile support and others. We're going for a profile-based implementation, instead of a regular CPU that can inherit RVA23, to allow future CPUs to use it internally as a starting base for their own extension sets. There's also a new 'rvserver-ref-1.0' flag that can be used to set the extensions in the command line for other CPUs, which can be used for testing/debugging purposes. Note that for all intents and purposes "riscv-server-ref" is a regular CPU and no, we're not trying to set a precedent of calling the riscv server platform spec a profile. [1] defines in rule SEE_020 that we must support at least 11 debug triggers (4 for insn address, 4 for insn load/store, 1 for icount, one for int, one for excp). We're going for the minimum. If more triggers are needed users can set any trigger amount with: -cpu riscv-server-ref,trigger-count=N Note that N must be <= 128. [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc Suggested-by: Icenowy Zheng Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Matheus Ferst Reviewed-by: Chao Liu --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 1a28f1369c..61234842e3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -42,6 +42,7 @@ #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") +#define TYPE_RISCV_CPU_RVSERVER_REF RISCV_CPU_TYPE_NAME("riscv-server-ref") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 185474a8cf..b5a75fbc1c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2417,11 +2417,35 @@ static RISCVCPUProfile RVA23S64 = { } }; +/* + * The riscv-server-ref spec isn't a profile per se but its + * CPU definition can be modelled as a profile that extends + * RVA23, with additional things on top of it, and allowing + * future CPUs to derive from it via + * ".profile = &RVServerRef1_0;". + */ +static RISCVCPUProfile RVServerRef1_0 = { + .s_parent = &RVA23S64, + .name = "rvserver-ref-1.0", + .satp_mode = VM_1_10_SV48, + .ext_offsets = { + CPU_CFG_OFFSET(ext_zkr), + CPU_CFG_OFFSET(ext_sdtrig), + CPU_CFG_OFFSET(ext_ssaia), + CPU_CFG_OFFSET(ext_ssccfg), + /* ssstrict is always enabled for PRIV_VER_1_12 */ + + RISCV_PROFILE_EXT_LIST_END + } +}; + + RISCVCPUProfile *riscv_profiles[] = { &RVA22U64, &RVA22S64, &RVA23U64, &RVA23S64, + &RVServerRef1_0, NULL, }; @@ -3759,6 +3783,13 @@ static const TypeInfo riscv_cpu_type_infos[] = { #endif ), + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSERVER_REF, TYPE_RISCV_BARE_CPU, + .profile = &RVServerRef1_0, + .misa_mxl_max = MXL_RV64, + .cfg.max_satp_mode = VM_1_10_SV57, + .num_triggers = 11, + ), + #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, .cfg.max_satp_mode = VM_1_10_SV57, -- 2.43.0