Re: [PATCH bpf-next v4 1/3] riscv, bpf: Remap BPF_REG_0 and RV_REG_TCC

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The block and inline assembly comments in `bpf_timed_may_goto.S` continue to reference `a5` as the mapped register for `BPF_REG_0`, which contradicts the updated code utilizing `t6`. This patch changes `a5` to `t6` in the instructions, but missed updating the corresponding comments.
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commit 3f2026164fcac1b3db2387eec49e58f20293243f
Author: Pu Lehui <pulehui@huawei.com>

riscv, bpf: Remap BPF_REG_0 and RV_REG_TCC

This commit remaps BPF_REG_0 to t6 and RV_REG_TCC to t5 to support BPF
stack arguments and unify calling conventions. Freeing up a5 and a6
allows bpf2bpf calls to pass extra arguments consistently with kfuncs.

> diff --git a/arch/riscv/net/bpf_timed_may_goto.S b/arch/riscv/net/bpf_timed_may_goto.S
> index 02c637d874205..ac41bf6dcb3d0 100644
> --- a/arch/riscv/net/bpf_timed_may_goto.S
> +++ b/arch/riscv/net/bpf_timed_may_goto.S
> @@ -21,7 +21,7 @@ SYM_FUNC_START(arch_bpf_timed_may_goto)
>  	addi	s0, sp, 8*SZREG
>  
>  	/* Save BPF registers R0-R5 (a5, a0-a4) */
> -	REG_S	a5, 5*SZREG(sp)
> +	REG_S	t6, 5*SZREG(sp)

[Severity: Low]
This isn't a bug, but should the inline comment above this instruction also
be updated to reflect that R0 is now mapped to t6 rather than a5?

Additionally, in the block comment at the beginning of
arch_bpf_timed_may_goto in arch/riscv/net/bpf_timed_may_goto.S, the text
still documents a5 as R0. Could these documentation references be updated to
match the code changes?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260905070409.4141522-1-pulehui@huaweicloud.com?part=1