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From: sashiko-bot@kernel.org
To: "Luo Jie" <jie.luo@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v4 07/12] clk: qcom: ipq-cmn-pll: Add PON reference clock support
Date: Sun, 06 Sep 2026 14:25:58 +0000	[thread overview]
Message-ID: <20260906142559.17FE91F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-7-aec5ed642f4f@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] clk_pon_clk_determine_rate() incorrectly fails valid rate requests due to rounding at bound edges.
--

commit 9a9a4823a8ebca7e3c30590799eb2ac41ada876e
Author: Luo Jie <jie.luo@oss.qualcomm.com>

clk: qcom: ipq-cmn-pll: Add PON reference clock support

This commit adds support for the PON reference clock to the IPQ CMN PLL driver.
It configures the clock to operate in either UNIPHY mode with a fixed 31.25 MHz
rate, or PON mode using an 8-bit divider derived from the parent rate.

> diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
> index 44d035870a89b..f12352a707f7a 100644
> --- a/drivers/clk/qcom/ipq-cmn-pll.c
> +++ b/drivers/clk/qcom/ipq-cmn-pll.c
[ ... ]
> +static int clk_pon_clk_determine_rate(struct clk_hw *hw,
> +				      struct clk_rate_request *req)
> +{
> +	unsigned long div, pon_rate, uniphy_rate = 31250000UL;
> +	bool uniphy_rate_valid, pon_rate_valid;
> +
> +	if (!req->rate || !req->best_parent_rate)
> +		return -EINVAL;
> +
> +	div = DIV64_U64_ROUND_CLOSEST((u64)req->best_parent_rate, req->rate);
> +
> +	/* Clamp to valid range (1-255) */
> +	div = clamp_t(unsigned long, div, 1, 255);
> +
> +	pon_rate = DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, div);
> +
> +	uniphy_rate_valid = uniphy_rate >= req->min_rate &&
> +			    uniphy_rate <= req->max_rate;
> +	pon_rate_valid = pon_rate >= req->min_rate &&
> +			 pon_rate <= req->max_rate;
> +
> +	if (!uniphy_rate_valid && !pon_rate_valid)
> +		return -EINVAL;

[Severity: High]
Will this logic incorrectly reject valid rate requests when the closest
divider falls slightly outside the boundaries due to rounding?

If a client restricts the bounds (e.g., via clk_set_min_rate), the requested
rate is clamped to the bounds. If calculating the closest divider for that
rate yields a frequency that barely misses the min_rate or max_rate bound, 
pon_rate_valid becomes false and this returns -EINVAL.

Should this code check adjacent dividers (such as div - 1 or div + 1) to see
if they yield a rate strictly within the requested bounds before giving up?

> +
> +	/* Pick whichever mode gets closer to the requested rate */
> +	if (uniphy_rate_valid && pon_rate_valid) {
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com?part=7

  reply	other threads:[~2026-09-06 14:25 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-06 14:18 [PATCH v4 00/12] clk: qcom: ipq-cmn-pll: Add IPQ5210 CMN PLL support Luo Jie
2026-09-06 14:18 ` [PATCH v4 01/12] clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data Luo Jie
2026-09-06 14:18 ` [PATCH v4 02/12] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoC Luo Jie
2026-09-06 14:18 ` [PATCH v4 03/12] clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags Luo Jie
2026-09-06 14:18 ` [PATCH v4 04/12] clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock Luo Jie
2026-09-06 14:18 ` [PATCH v4 05/12] clk: qcom: ipq-cmn-pll: Add NSS clock support Luo Jie
2026-09-06 14:18 ` [PATCH v4 06/12] clk: qcom: ipq-cmn-pll: Add PPE " Luo Jie
2026-09-06 14:18 ` [PATCH v4 07/12] clk: qcom: ipq-cmn-pll: Add PON reference " Luo Jie
2026-09-06 14:25   ` sashiko-bot [this message]
2026-09-08  3:28     ` Jie Luo
2026-09-06 14:18 ` [PATCH v4 08/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW " Luo Jie
2026-09-06 14:18 ` [PATCH v4 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks Luo Jie
2026-09-06 14:18 ` [PATCH v4 10/12] clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210 Luo Jie
2026-09-06 14:18 ` [PATCH v4 11/12] arm64: dts: qcom: ipq5210: Add CMN PLL device node Luo Jie
2026-09-06 14:18 ` [PATCH v4 12/12] arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock Luo Jie

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