From: Hemanth Selam <hemanth.selam@gmail.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
sparclinux@vger.kernel.org
Subject: [PATCH 06/14] sparc: kernel: fix typo "upto" in comment
Date: Mon, 7 Sep 2026 12:25:14 +0530 [thread overview]
Message-ID: <20260907065514.23930-1-hemanth.selam@gmail.com> (raw)
Correct "upto" to "up to", reported by scripts/checkpatch.pl using the
misspelling list in scripts/spelling.txt. Only touches comments, no code
changes.
Assisted-by: Cursor:claude-opus-5
Signed-off-by: Hemanth Selam <hemanth.selam@gmail.com>
---
arch/sparc/kernel/perf_event.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 0ce4ae343531..f4b7a9dfc90a 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -36,7 +36,7 @@
* 32-bit counters which can generate overflow interrupts on the
* transition from 0xffffffff to 0.
*
- * All chips upto and including SPARC-T3 have two performance
+ * All chips up to and including SPARC-T3 have two performance
* counters. The two 32-bit counters are accessed in one go using a
* single 64-bit register.
*
reply other threads:[~2026-09-07 6:55 UTC|newest]
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