From: sashiko-bot@kernel.org
To: "Devendra K Verma" <devverma@amd.com>
Cc: dmaengine@vger.kernel.org, vkoul@kernel.org, Frank.Li@kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH RESEND v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC
Date: Mon, 07 Sep 2026 10:19:48 +0000 [thread overview]
Message-ID: <20260907101949.4D0521F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260907101213.1917064-2-devverma@amd.com>
> As per, 'Designware Cores PCI Express DM Controller - Reference
> Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports
> the channel separation mechanisms. Basically, the HDMA IP allows
> the user to configure the separation between DMA channel
> registers and retrieve it via the VSEC capability mentioned
> above.
>
> HDMA IP supports the channel register space separation from
> 256B to 32KB. Default supported size is 256B.
>
> Signed-off-by: Devendra K Verma <devverma@amd.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260907101213.1917064-1-devverma@amd.com?part=1
next prev parent reply other threads:[~2026-09-07 10:19 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 10:12 [PATCH RESEND v5 0/2] CPM6 Channel Separation Support Devendra K Verma
2026-09-07 10:12 ` [PATCH RESEND v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC Devendra K Verma
2026-09-07 10:19 ` sashiko-bot [this message]
2026-09-07 10:12 ` [PATCH RESEND v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation Devendra K Verma
2026-09-07 10:24 ` sashiko-bot
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