From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: Antti Laakso <antti.laakso@linux.intel.com>,
sarang.sapre@intel.com, daxing.li@intel.com,
ong.hock.yu@intel.com
Subject: [PATCH v4 43/45] media: ipu6: Add ipu7.5 mmu initialization data
Date: Mon, 7 Sep 2026 14:30:02 +0300 [thread overview]
Message-ID: <20260907113004.2489993-44-sakari.ailus@linux.intel.com> (raw)
In-Reply-To: <20260907113004.2489993-1-sakari.ailus@linux.intel.com>
From: Antti Laakso <antti.laakso@linux.intel.com>
The ipu7.5 mmu is different compared to ipu7.
Signed-off-by: Antti Laakso <antti.laakso@linux.intel.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c | 261 ++++++++++++++++++++-
drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h | 99 ++++++++
2 files changed, 359 insertions(+), 1 deletion(-)
diff --git a/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c b/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c
index 3cd9a818733c..c9b015e89ee6 100644
--- a/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c
+++ b/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.c
@@ -431,6 +431,250 @@ static struct ipu7_mmu_hw ipu7_psys_mmu_hwdata[] = {
},
};
+static struct ipu7_mmu_hw ipu7p5_isys_mmu_hwdata[] = {
+ {
+ .name = "IS_FW_RD",
+ .offset = IPU7P5_IS_MMU_FW_RD_OFFSET,
+ .zlx_offset = IPU7P5_IS_ZLX_UC_RD_OFFSET,
+ .uao_offset = IPU7P5_IS_UAO_UC_RD_OFFSET,
+ .info_bits = 0x20005101,
+ .refill = 0x00002726,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU7P5_IS_MMU_FW_RD_L1_BLOCKNR_REG,
+ .l2_block = IPU7P5_IS_MMU_FW_RD_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU7P5_IS_MMU_FW_RD_STREAM_NUM,
+ .nr_l2streams = IPU7P5_IS_MMU_FW_RD_STREAM_NUM,
+ .l1_block_sz = { 0x0, 0x8, 0xa },
+ .l2_block_sz = { 0x0, 0x2, 0x4 },
+ .zlx_nr = IPU7P5_IS_ZLX_UC_RD_NUM,
+ .zlx_axi_pool = { 0x00000f30 },
+ .zlx_en = { 0, 1, 0, 0 },
+ .zlx_conf = { 0x0 },
+ .uao_p_num = IPU7P5_IS_UAO_UC_RD_PLANENUM,
+ .uao_p2tlb = { 0x49, 0x4c, 0x4d, 0x0 },
+ },
+ {
+ .name = "IS_FW_WR",
+ .offset = IPU7P5_IS_MMU_FW_WR_OFFSET,
+ .zlx_offset = IPU7P5_IS_ZLX_UC_WR_OFFSET,
+ .uao_offset = IPU7P5_IS_UAO_UC_WR_OFFSET,
+ .info_bits = 0x20005001,
+ .refill = 0x00002524,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU7P5_IS_MMU_FW_WR_L1_BLOCKNR_REG,
+ .l2_block = IPU7P5_IS_MMU_FW_WR_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU7P5_IS_MMU_FW_WR_STREAM_NUM,
+ .nr_l2streams = IPU7P5_IS_MMU_FW_WR_STREAM_NUM,
+ .l1_block_sz = { 0x0, 0x8, 0xa },
+ .l2_block_sz = { 0x0, 0x2, 0x4 },
+ .zlx_nr = IPU7P5_IS_ZLX_UC_WR_NUM,
+ .zlx_axi_pool = { 0x00000f20 },
+ .zlx_en = { 0, 1, 1, 0 },
+ .zlx_conf = { 0x0, 0x00010101, 0x00010101, 0x0 },
+ .uao_p_num = IPU7P5_IS_UAO_UC_WR_PLANENUM,
+ .uao_p2tlb = { 0x49, 0x4a, 0x4b, 0x0 },
+ },
+ {
+ .name = "IS_DATA_WR_ISOC",
+ .offset = IPU7P5_IS_MMU_M0_OFFSET,
+ .zlx_offset = IPU7P5_IS_ZLX_M0_OFFSET,
+ .uao_offset = IPU7P5_IS_UAO_M0_WR_OFFSET,
+ .info_bits = 0x20004e01,
+ .refill = 0x00002120,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU7P5_IS_MMU_M0_L1_BLOCKNR_REG,
+ .l2_block = IPU7P5_IS_MMU_M0_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU7P5_IS_MMU_M0_STREAM_NUM,
+ .nr_l2streams = IPU7P5_IS_MMU_M0_STREAM_NUM,
+ .l1_block_sz = { 0x0, 0x2, 0x4, 0x6, 0x8, 0xa, 0xc, 0xe, 0x10,
+ 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x01e },
+ .l2_block_sz = { 0x0, 0x2, 0x4, 0x6, 0x8, 0xa, 0xc, 0xe, 0x10,
+ 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e },
+ .zlx_nr = IPU7P5_IS_ZLX_M0_NUM,
+ .zlx_axi_pool = { 0x00000f10 },
+ .zlx_en = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 },
+ .zlx_conf = { 0x00010103, 0x00010103, 0x00010103, 0x00010103,
+ 0x00010103, 0x00010103, 0x00010103, 0x00010103,
+ 0x00010103, 0x00010103, 0x00010103, 0x00010103,
+ 0x00010103, 0x00010103, 0x00010103, 0x00010103 },
+ .uao_p_num = IPU7P5_IS_UAO_M0_WR_PLANENUM,
+ .uao_p2tlb = { 0x00000041, 0x00000042, 0x00000043, 0x00000044,
+ 0x00000041, 0x00000042, 0x00000043, 0x00000044,
+ 0x00000041, 0x00000042, 0x00000043, 0x00000044,
+ 0x00000041, 0x00000042, 0x00000043, 0x00000044 },
+ },
+ {
+ .name = "IS_DATA_WR_SNOOP",
+ .offset = IPU7P5_IS_MMU_M1_OFFSET,
+ .zlx_offset = IPU7P5_IS_ZLX_M1_OFFSET,
+ .uao_offset = IPU7P5_IS_UAO_M1_WR_OFFSET,
+ .info_bits = 0x20004f01,
+ .refill = 0x00002322,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU7P5_IS_MMU_M1_L1_BLOCKNR_REG,
+ .l2_block = IPU7P5_IS_MMU_M1_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU7P5_IS_MMU_M1_STREAM_NUM,
+ .nr_l2streams = IPU7P5_IS_MMU_M1_STREAM_NUM,
+ .l1_block_sz = { 0x0, 0x2, 0x4, 0x6, 0x8, 0xa, 0xc, 0xe, 0x10,
+ 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e },
+ .l2_block_sz = { 0x0, 0x2, 0x4, 0x6, 0x8, 0xa, 0xc, 0xe, 0x10,
+ 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e },
+ .zlx_nr = IPU7P5_IS_ZLX_M1_NUM,
+ .zlx_axi_pool = { 0x00000f20 },
+ .zlx_en = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 },
+ .zlx_conf = { 0x00010103, 0x00010103, 0x00010103, 0x00010103,
+ 0x00010103, 0x00010103, 0x00010103, 0x00010103,
+ 0x00010103, 0x00010103, 0x00010103, 0x00010103,
+ 0x00010103, 0x00010103, 0x00010103, 0x00010103 },
+ .uao_p_num = IPU7P5_IS_UAO_M1_WR_PLANENUM,
+ .uao_p2tlb = { 0x00000045, 0x00000046, 0x00000047, 0x00000048,
+ 0x00000045, 0x00000046, 0x00000047, 0x00000048,
+ 0x00000045, 0x00000046, 0x00000047, 0x00000048,
+ 0x00000045, 0x00000046, 0x00000047, 0x00000048 },
+ },
+};
+
+static struct ipu7_mmu_hw ipu7p5_psys_mmu_hwdata[] = {
+ {
+ .name = "PS_FW_RD",
+ .offset = IPU7P5_PS_MMU_FW_RD_OFFSET,
+ .zlx_offset = IPU7P5_PS_ZLX_FW_RD_OFFSET,
+ .uao_offset = IPU7P5_PS_UAO_FW_RD_OFFSET,
+ .info_bits = 0x20004001,
+ .refill = 0x00002726,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU7P5_PS_MMU_FW_RD_L1_BLOCKNR_REG,
+ .l2_block = IPU7P5_PS_MMU_FW_RD_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU7P5_PS_MMU_FW_RD_STREAM_NUM,
+ .nr_l2streams = IPU7P5_PS_MMU_FW_RD_STREAM_NUM,
+ .l1_block_sz = { 0x00, 0x08, 0x0a, 0x0c, 0x0d, 0x0f, 0x11,
+ 0x12, 0x13, 0x14, 0x16, 0x18, 0x19, 0x1a,
+ 0x1a, 0x1a },
+ .l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c,
+ 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a,
+ 0x1c, 0x1e },
+ .zlx_nr = IPU7P5_PS_ZLX_FW_RD_NUM,
+ .zlx_axi_pool = { 0x00000f30 },
+ .zlx_en = { 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 },
+ .zlx_conf = { 0x00000000, 0x00010101, 0x00000000, 0x00000000,
+ 0x00010101, 0x00010101, 0x00000000, 0x00000000,
+ 0x00000000, 0x00010101, 0x00010101, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ .uao_p_num = IPU7P5_PS_UAO_FW_RD_PLANENUM,
+ .uao_p2tlb = { 0x2e, 0x35, 0x36, 0x31, 0x37, 0x38, 0x39, 0x32,
+ 0x33, 0x3a, 0x3b, 0x3c, 0x34, 0x00, 0x00, 0x00 },
+ },
+ {
+ .name = "PS_FW_WR",
+ .offset = IPU7P5_PS_MMU_FW_WR_OFFSET,
+ .zlx_offset = IPU7P5_PS_ZLX_FW_WR_OFFSET,
+ .uao_offset = IPU7P5_PS_UAO_FW_WR_OFFSET,
+ .info_bits = 0x20003e01,
+ .refill = 0x00002322,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU7P5_PS_MMU_FW_WR_L1_BLOCKNR_REG,
+ .l2_block = IPU7P5_PS_MMU_FW_WR_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU7P5_PS_MMU_FW_WR_STREAM_NUM,
+ .nr_l2streams = IPU7P5_PS_MMU_FW_WR_STREAM_NUM,
+ .l1_block_sz = { 0x00, 0x08, 0x0a, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
+ 0x10, 0x10 },
+ .l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
+ 0x10, 0x12 },
+ .zlx_nr = IPU7P5_PS_ZLX_FW_WR_NUM,
+ .zlx_axi_pool = { 0x00000f20 },
+ .zlx_en = { 0, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+ .zlx_conf = { 0x00000000, 0x00010101, 0x00010101, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000 },
+ .uao_p_num = IPU7P5_PS_UAO_FW_WR_PLANENUM,
+ .uao_p2tlb = { 0x0000002e, 0x0000002f, 0x00000030, 0x00000031,
+ 0x00000032, 0x00000033, 0x00000034, 0x00000000,
+ 0x00000000, 0x00000000 },
+ },
+ {
+ .name = "PS_DATA_RD",
+ .offset = IPU7P5_PS_MMU_SRT_RD_OFFSET,
+ .zlx_offset = IPU7P5_PS_ZLX_DATA_RD_OFFSET,
+ .uao_offset = IPU7P5_PS_UAO_SRT_RD_OFFSET,
+ .info_bits = 0x20003f01,
+ .refill = 0x00002524,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU7P5_PS_MMU_SRT_RD_L1_BLOCKNR_REG,
+ .l2_block = IPU7P5_PS_MMU_SRT_RD_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU7P5_PS_MMU_SRT_RD_STREAM_NUM,
+ .nr_l2streams = IPU7P5_PS_MMU_SRT_RD_STREAM_NUM,
+ .l1_block_sz = { 0x00, 0x04, 0x06, 0x08, 0x0b, 0x0d, 0x0f, 0x13,
+ 0x17, 0x19, 0x1b, 0x1d, 0x1f, 0x2b, 0x33, 0x3f,
+ 0x47, 0x49, 0x4b, 0x4c, 0x4d, 0x4e },
+ .l2_block_sz = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
+ 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
+ 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a },
+ .zlx_nr = IPU7P5_PS_ZLX_DATA_RD_NUM,
+ .zlx_axi_pool = { 0x00000f30 },
+ .zlx_en = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 0, 0, 0, 0 },
+ .zlx_conf = { 0x00030303, 0x00010101, 0x00010101, 0x00030202,
+ 0x00010101, 0x00010101, 0x00030303, 0x00030303,
+ 0x00010101, 0x00030800, 0x00030500, 0x00020101,
+ 0x00042000, 0x00031000, 0x00042000, 0x00031000,
+ 0x00020400, 0x00010101, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000 },
+ .uao_p_num = IPU7P5_PS_UAO_SRT_RD_PLANENUM,
+ .uao_p2tlb = { 0x0000001c, 0x0000001d, 0x0000001e, 0x0000001f,
+ 0x00000020, 0x00000021, 0x00000022, 0x00000023,
+ 0x00000024, 0x00000025, 0x00000026, 0x00000027,
+ 0x00000028, 0x00000029, 0x0000002a, 0x0000002b,
+ 0x0000002c, 0x0000002d, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000 },
+ },
+ {
+ .name = "PS_DATA_WR",
+ .offset = IPU7P5_PS_MMU_SRT_WR_OFFSET,
+ .zlx_offset = IPU7P5_PS_ZLX_DATA_WR_OFFSET,
+ .uao_offset = IPU7P5_PS_UAO_SRT_WR_OFFSET,
+ .info_bits = 0x20003d01,
+ .refill = 0x00002120,
+ .collapse_en_bitmap = 0x1,
+ .at_sp_arb_cfg = 0x1,
+ .l1_block = IPU7P5_PS_MMU_SRT_WR_L1_BLOCKNR_REG,
+ .l2_block = IPU7P5_PS_MMU_SRT_WR_L2_BLOCKNR_REG,
+ .nr_l1streams = IPU7P5_PS_MMU_SRT_WR_STREAM_NUM,
+ .nr_l2streams = IPU7P5_PS_MMU_SRT_WR_STREAM_NUM,
+ .l1_block_sz = { 0x00, 0x02, 0x06, 0x0a, 0x0c, 0x0e, 0x10, 0x12,
+ 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22,
+ 0x24, 0x28, 0x2a, 0x36, 0x3e, 0x40, 0x42, 0x4e,
+ 0x56, 0x5c, 0x68, 0x70, 0x76, 0x77, 0x78, 0x79 },
+ .l2_block_sz = { 0x00, 0x02, 0x06, 0x0a, 0x0c, 0x0e, 0x10, 0x12,
+ 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22,
+ 0x24, 0x28, 0x2a, 0x36, 0x3e, 0x40, 0x42, 0x4e,
+ 0x56, 0x5c, 0x68, 0x70, 0x76, 0x77, 0x78, 0x79 },
+ .zlx_nr = IPU7P5_PS_ZLX_DATA_WR_NUM,
+ .zlx_axi_pool = { 0x00000f50 },
+ .zlx_en = { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
+ .zlx_conf = { 0x00010102, 0x00030103, 0x00030103, 0x00010101,
+ 0x00010101, 0x00030101, 0x00010101, 0x38010101,
+ 0x00000000, 0x00000000, 0x38010101, 0x38010101,
+ 0x38010101, 0x38010101, 0x38010101, 0x38010101,
+ 0x00030303, 0x00010101, 0x00042000, 0x00031000,
+ 0x00010101, 0x00010101, 0x00042000, 0x00031000,
+ 0x00031000, 0x00042000, 0x00031000, 0x00031000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000 },
+ .uao_p_num = IPU7P5_PS_UAO_SRT_WR_PLANENUM,
+ .uao_p2tlb = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x18, 0x19, 0x1a, 0x1b, 0x00, 0x00, 0x00, 0x00 },
+ },
+};
+
static const struct ipu7_mmu_hwdata ipu7_mmu_hwdata_lookup[IPU_SUBSYS_NUM] = {
[IPU_PSYS] = {
.hwdata = ipu7_psys_mmu_hwdata,
@@ -442,6 +686,17 @@ static const struct ipu7_mmu_hwdata ipu7_mmu_hwdata_lookup[IPU_SUBSYS_NUM] = {
},
};
+static const struct ipu7_mmu_hwdata ipu7p5_mmu_hwdata_lookup[IPU_SUBSYS_NUM] = {
+ [IPU_PSYS] = {
+ .hwdata = ipu7p5_psys_mmu_hwdata,
+ .nr_mmus = ARRAY_SIZE(ipu7p5_psys_mmu_hwdata),
+ },
+ [IPU_ISYS] = {
+ .hwdata = ipu7p5_isys_mmu_hwdata,
+ .nr_mmus = ARRAY_SIZE(ipu7p5_isys_mmu_hwdata),
+ },
+};
+
static void __ipu7_tlb_invalidate(struct ipu6_mmu *mmu)
{
struct ipu7_mmu_hw *mmu_hw = mmu->ipu7_mmu_hw;
@@ -561,13 +816,17 @@ static int __ipu7_mmu_hw_init(struct ipu6_mmu *mmu)
static int __ipu7_mmu_init_hw_data(struct ipu6_mmu *mmu, struct device *dev,
void __iomem *base)
{
- const struct ipu7_mmu_hwdata *lookup = ipu7_mmu_hwdata_lookup;
+ struct ipu6_device *isp = pci_get_drvdata(to_pci_dev(dev));
+ const struct ipu7_mmu_hwdata *lookup;
struct ipu7_mmu_hw *mmu_hw, *src;
unsigned int i, nr_mmus;
if (mmu->mmid >= IPU_SUBSYS_NUM)
return -EINVAL;
+ lookup = IS_IPU7P5(isp) ? ipu7p5_mmu_hwdata_lookup :
+ ipu7_mmu_hwdata_lookup;
+
src = lookup[mmu->mmid].hwdata;
nr_mmus = lookup[mmu->mmid].nr_mmus;
diff --git a/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h b/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h
index 68663057138a..ba31ed31b245 100644
--- a/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h
+++ b/drivers/media/pci/intel/ipu6/ipu7-mmu-hw.h
@@ -114,6 +114,105 @@
#define IPU7_PS_ZLX_FW_RD_NUM 16
#define IPU7_PS_ZLX_FW_WR_NUM 10
+/* IPU7P5 */
+/* IS MMU Cmd RD */
+#define IPU7P5_IS_MMU_FW_RD_OFFSET 0x274000
+#define IPU7P5_IS_MMU_FW_RD_STREAM_NUM 3
+#define IPU7P5_IS_MMU_FW_RD_L1_BLOCKNR_REG 0x54
+#define IPU7P5_IS_MMU_FW_RD_L2_BLOCKNR_REG 0x60
+
+/* IS MMU Cmd WR */
+#define IPU7P5_IS_MMU_FW_WR_OFFSET 0x275000
+#define IPU7P5_IS_MMU_FW_WR_STREAM_NUM 3
+#define IPU7P5_IS_MMU_FW_WR_L1_BLOCKNR_REG 0x54
+#define IPU7P5_IS_MMU_FW_WR_L2_BLOCKNR_REG 0x60
+
+/* IS MMU Data WR Snoop */
+#define IPU7P5_IS_MMU_M0_OFFSET 0x276000
+#define IPU7P5_IS_MMU_M0_STREAM_NUM 16
+#define IPU7P5_IS_MMU_M0_L1_BLOCKNR_REG 0x54
+#define IPU7P5_IS_MMU_M0_L2_BLOCKNR_REG 0x94
+
+/* IS MMU Data WR ISOC */
+#define IPU7P5_IS_MMU_M1_OFFSET 0x277000
+#define IPU7P5_IS_MMU_M1_STREAM_NUM 16
+#define IPU7P5_IS_MMU_M1_L1_BLOCKNR_REG 0x54
+#define IPU7P5_IS_MMU_M1_L2_BLOCKNR_REG 0x94
+
+/* PS MMU FW RD */
+#define IPU7P5_PS_MMU_FW_RD_OFFSET 0x148000
+#define IPU7P5_PS_MMU_FW_RD_STREAM_NUM 16
+#define IPU7P5_PS_MMU_FW_RD_L1_BLOCKNR_REG 0x54
+#define IPU7P5_PS_MMU_FW_RD_L2_BLOCKNR_REG 0x94
+
+/* PS MMU FW WR */
+#define IPU7P5_PS_MMU_FW_WR_OFFSET 0x149000
+#define IPU7P5_PS_MMU_FW_WR_STREAM_NUM 10
+#define IPU7P5_PS_MMU_FW_WR_L1_BLOCKNR_REG 0x54
+#define IPU7P5_PS_MMU_FW_WR_L2_BLOCKNR_REG 0x7c
+
+/* PS MMU FW Data RD VC0 */
+#define IPU7P5_PS_MMU_SRT_RD_OFFSET 0x14a000
+#define IPU7P5_PS_MMU_SRT_RD_STREAM_NUM 22
+#define IPU7P5_PS_MMU_SRT_RD_L1_BLOCKNR_REG 0x54
+#define IPU7P5_PS_MMU_SRT_RD_L2_BLOCKNR_REG 0xac
+
+/* PS MMU FW Data WR VC0 */
+#define IPU7P5_PS_MMU_SRT_WR_OFFSET 0x14b000
+#define IPU7P5_PS_MMU_SRT_WR_STREAM_NUM 32
+#define IPU7P5_PS_MMU_SRT_WR_L1_BLOCKNR_REG 0x54
+#define IPU7P5_PS_MMU_SRT_WR_L2_BLOCKNR_REG 0xd4
+
+/* IS UAO UC RD */
+#define IPU7P5_IS_UAO_UC_RD_OFFSET 0x27c000
+#define IPU7P5_IS_UAO_UC_RD_PLANENUM 4
+
+/* IS UAO UC WR */
+#define IPU7P5_IS_UAO_UC_WR_OFFSET 0x27d000
+#define IPU7P5_IS_UAO_UC_WR_PLANENUM 4
+
+/* IS UAO M0 WR */
+#define IPU7P5_IS_UAO_M0_WR_OFFSET 0x27e000
+#define IPU7P5_IS_UAO_M0_WR_PLANENUM 16
+
+/* IS UAO M1 WR */
+#define IPU7P5_IS_UAO_M1_WR_OFFSET 0x27f000
+#define IPU7P5_IS_UAO_M1_WR_PLANENUM 16
+
+/* PS UAO FW RD */
+#define IPU7P5_PS_UAO_FW_RD_OFFSET 0x156000
+#define IPU7P5_PS_UAO_FW_RD_PLANENUM 16
+
+/* PS UAO FW WR */
+#define IPU7P5_PS_UAO_FW_WR_OFFSET 0x157000
+#define IPU7P5_PS_UAO_FW_WR_PLANENUM 10
+
+/* PS UAO SRT RD */
+#define IPU7P5_PS_UAO_SRT_RD_OFFSET 0x154000
+#define IPU7P5_PS_UAO_SRT_RD_PLANENUM 22
+
+/* PS UAO SRT WR */
+#define IPU7P5_PS_UAO_SRT_WR_OFFSET 0x155000
+#define IPU7P5_PS_UAO_SRT_WR_PLANENUM 32
+
+#define IPU7P5_IS_ZLX_UC_RD_OFFSET 0x278000
+#define IPU7P5_IS_ZLX_UC_WR_OFFSET 0x279000
+#define IPU7P5_IS_ZLX_M0_OFFSET 0x27a000
+#define IPU7P5_IS_ZLX_M1_OFFSET 0x27b000
+#define IPU7P5_IS_ZLX_UC_RD_NUM 4
+#define IPU7P5_IS_ZLX_UC_WR_NUM 4
+#define IPU7P5_IS_ZLX_M0_NUM 16
+#define IPU7P5_IS_ZLX_M1_NUM 16
+
+#define IPU7P5_PS_ZLX_DATA_RD_OFFSET 0x14e000
+#define IPU7P5_PS_ZLX_DATA_WR_OFFSET 0x14f000
+#define IPU7P5_PS_ZLX_FW_RD_OFFSET 0x150000
+#define IPU7P5_PS_ZLX_FW_WR_OFFSET 0x151000
+#define IPU7P5_PS_ZLX_DATA_RD_NUM 22
+#define IPU7P5_PS_ZLX_DATA_WR_NUM 32
+#define IPU7P5_PS_ZLX_FW_RD_NUM 16
+#define IPU7P5_PS_ZLX_FW_WR_NUM 10
+
struct ipu7_mmu_hw {
char name[32];
--
2.47.3
next prev parent reply other threads:[~2026-09-07 11:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-07 11:29 [PATCH v4 00/45] media: ipu6: Add support for ipu7 hardware Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 01/45] media: ipu6: Add helpers for IPU runtime variation Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 02/45] media: ipu6: Rename pointer to firmware context Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 03/45] media: ipu6: Rename buttress_ipc pointer Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 04/45] media: ipu6: Remove duplicate warnings in cpd validation Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 05/45] media: ipu6: Remove unused ipu6 firmware struct Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 06/45] media: ipu6: Cleanup ipu6_mmu_init() Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 07/45] media: ipu6: Simplify firmware com arguments Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 08/45] media: ipu6: Add helper to identify ipu7 Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 09/45] media: ipu6: Prepare buttress for ipu7 support Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 10/45] media: ipu6: Use single struct for registers Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 11/45] media: ipu6: Rename IPU subsys ID Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 12/45] media: ipu6: Add ipu7 buttress support Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 13/45] media: ipu6: Prepare mmu driver for hw variation Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 14/45] media: ipu6: Add ipu7 mmu support Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 15/45] media: ipu6: Add ipu7 cpd handling Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 16/45] media: ipu6: Add check for pkg_dir before freeing Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 17/45] media: ipu6: Rename isys fw msg union Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 18/45] media: ipu6: Move isys isr handlers to fw file Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 19/45] media: ipu6: Move hw specific buffer handling down Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 20/45] media: ipu6: Isolate hw specific buffer handling Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 21/45] media: ipu6: Add isys firmware ops Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 22/45] media: ipu6: Add ipu7 fw start/stop functionality Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 23/45] media: ipu6: Add ipu7 fw com methods Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 24/45] media: ipu6: Add ipu7 fw isys ops Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 25/45] media: ipu6: Add ipu7 csi2 register definitions Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 26/45] media: ipu6: Add ipu7 isr handler Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 27/45] media: ipu6: Add ipu7 csi phy driver Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 28/45] media: ipu6: Split ipu6 csi2 stream enable/disable Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 29/45] media: ipu6: Add support for ipu7 csi2 receiver Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 30/45] media: ipu6: Parse bus type for ipu7 Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 31/45] media: ipu6: Enable ipu7 isys interrupts Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 32/45] media: ipu6: Skip watermark configuration for ipu7 Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 33/45] media: ipu6: The SPC init is valid only for ipu6 Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 34/45] media: ipu6: The VC arbitration mechanism is ipu6 only Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 35/45] media: ipu6: Move buttress mem alloc out from probe Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 36/45] media: ipu6: Read correct SKU ID for ipu7 Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 37/45] media: ipu6: Add support for fixed iova region Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 38/45] media: ipu6: Make fw mapping function reusable Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 39/45] media: ipu6: Move isys fw mapping to pci_probe Sakari Ailus
2026-09-07 11:29 ` [PATCH v4 40/45] media: ipu6: Map ipu7 firmware Sakari Ailus
2026-09-07 11:30 ` [PATCH v4 41/45] media: ipu6: Set model name for ipu7 Sakari Ailus
2026-09-07 11:30 ` [PATCH v4 42/45] media: ipu6: Add ipu7.5 buttress support Sakari Ailus
2026-09-07 11:30 ` Sakari Ailus [this message]
2026-09-07 11:30 ` [PATCH v4 44/45] media: ipu6: Enable support for IPU 7 and IPU 7.5 Sakari Ailus
2026-09-07 11:30 ` [PATCH v4 45/45] staging: media: ipu7: Update TODO file Sakari Ailus
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