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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339aa37dbdsm23747143eec.11.2026.09.07.05.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 05:21:34 -0700 (PDT) From: Wei Deng To: Manivannan Sadhasivam , Bartosz Golaszewski Cc: linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_chezhou@quicinc.com, cheng.jiang@oss.qualcomm.com, shuai.zhang@oss.qualcomm.com, jinwang.li@oss.qualcomm.com, xiuzhuo.shang@oss.qualcomm.com, mengshi.wu@oss.qualcomm.com Subject: [PATCH] power: sequencing: pwrseq-pcie-m2: Support PCIe switch topologies Date: Mon, 7 Sep 2026 17:51:29 +0530 Message-Id: <20260907122129.1577279-1-wei.deng@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDEzNyBTYWx0ZWRfX2RxpIm3gcWIO INZTM0zweRZg9P67ja8K6/B9UZFfZ0Ob3bS0S6h0rtrMh0ls4fd9T6T/T+hGvpcp9DUJ3+5MudI CVMhjbFYnqqlqRQAgOEkHSqM9hgb0lTUnHR/1dbb+yfW3oDLo8R/IAX1ZEJxj8Nj0N/PWUvnpNc DfP6z9Tr3HS38WfXsCPUcE7+mRp+9J2kQm2MfyZgFWXS8CNcvvebq5jur/RBeSX3stDT42ldvwd U0VdFyjUjFSV1yxfGCpqrXMQiIwSyrpxFx3OERTgnH0yyDfa8u5ueahPj+Zq7k3LX1X+eOdjRSi Dv+EWJE+g0UkAacbYDRsy0g0xYBiImR7AiywNuY4GjmM4zygoUnYBLSJzPu5hj58LdN6QnER7gJ y7iNQgtsZZzHautOsiuj7qmzT83Mkr88v4VhpcmvGUuGX1QaiLOc1w8lvLCbp2pxPKLaC2BoIQ5 ZDBJpxOOAStt+P+72Kw== X-Proofpoint-GUID: dEmLUY5UoKNOxARF4Uo9kSMxpe2R78on X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDEzNyBTYWx0ZWRfX+PXXRg5KL0vN DAHFG/ZptiVR/9Ruz4YShiLWvuXXkCRcQ8PBg27uralAgvrT+s9Jutib2zCQqbRkeLC0LUeGygT tD3S7LgqHGmlgXszpV1fWT4FEiTnUu0= X-Authority-Analysis: v=2.4 cv=daOwG3Xe c=1 sm=1 tr=0 ts=6a9eac50 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=RVAIDergrmqZ-0WmEXkA:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-ORIG-GUID: dEmLUY5UoKNOxARF4Uo9kSMxpe2R78on X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_03,2026-09-07_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070137 The PCI parent OF node check in pwrseq_pcie_m2_notify() and pwrseq_pcie_m2_create_serdev() only looks at the immediate parent of the PCI endpoint device. This fails when a PCIe switch inserts one or more intermediate bridges between the root port and the endpoint. For example, on lemans-evk with IFP Mezzanine board, the Toshiba TC9562 PCIe switch creates two bridge devices (upstream and downstream ports) without OF nodes, so the WCN6855 BT device appears at depth 3 and its immediate parent has of_node=NULL. Add a helper pwrseq_pcie_m2_pci_parent_matches() that walks the PCI parent chain upward until it finds a device whose OF node matches the expected connector port node, or reaches a non-PCI device. Replace both single-level checks with this helper to handle arbitrary PCIe switch depths. Signed-off-by: Wei Deng --- drivers/power/sequencing/pwrseq-pcie-m2.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequencing/pwrseq-pcie-m2.c index de9848a9a9f1..82ba309ba5f3 100644 --- a/drivers/power/sequencing/pwrseq-pcie-m2.c +++ b/drivers/power/sequencing/pwrseq-pcie-m2.c @@ -376,6 +376,21 @@ static void pwrseq_pcie_m2_remove_serdev(struct pwrseq_pcie_m2_ctx *ctx, mutex_unlock(&ctx->list_lock); } +static bool pwrseq_pcie_m2_pci_parent_matches(struct pci_dev *pdev, + struct device_node *pci_parent) +{ + struct device *dev = pdev->dev.parent; + + while (dev) { + if (dev->of_node == pci_parent) + return true; + if (!dev_is_pci(dev)) + break; + dev = dev->parent; + } + return false; +} + static int pwrseq_pcie_m2_notify(struct notifier_block *nb, unsigned long action, void *data) { @@ -390,7 +405,7 @@ static int pwrseq_pcie_m2_notify(struct notifier_block *nb, unsigned long action */ struct device_node *pci_parent __free(device_node) = of_graph_get_remote_node(dev_of_node(ctx->dev), 0, 0); - if (!pci_parent || (pci_parent != pdev->dev.parent->of_node)) + if (!pci_parent || !pwrseq_pcie_m2_pci_parent_matches(pdev, pci_parent)) return NOTIFY_DONE; switch (action) { @@ -464,7 +479,7 @@ static int pwrseq_pcie_m2_create_serdev(struct pwrseq_pcie_m2_ctx *ctx) /* Create serdev for existing PCI devices if required */ for_each_pci_dev(pdev) { - if (!pdev->dev.parent || pci_parent != pdev->dev.parent->of_node) + if (!pwrseq_pcie_m2_pci_parent_matches(pdev, pci_parent)) continue; if (!pci_match_id(pwrseq_m2_pci_ids, pdev)) -- 2.34.1