From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFB91C79FAA for ; Tue, 8 Sep 2026 06:39:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F54010E9F5; Tue, 8 Sep 2026 06:39:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XkxuJj7L"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id A99BC10E9ED; Tue, 8 Sep 2026 06:39:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788849556; x=1820385556; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tYHKfLC3LMsPBep3Ltp/DdS7QBX0r1EWHKt1EWOuCeA=; b=XkxuJj7Ll8mzhrVPgX/L3fFjl1Z7cWLmb/mB+8if/f2bnynbW2JRgEjq B7gVNlTGcA2TCcUeDCIQYMB4RKHnRkj0/e2cb/bnTQcdcqsHbUgajjTKN AmcH0Gcf+cUcLvXdIc3fLGkq01CK1g9ZzPdyOl9hFO4ExHnzlUr3cMUY5 nOcnZJ/zw7ILHcAs3YtyTVBs/PoVAp7OzpNPqSx77BiPpXD0ugk8R8eQG BkOCqOUpP3m+b0ez0wTWHYxoHy1Rr7nB3j6Unl3Bsm2X7X9SPMONSMLoV amgDLUn2Mt78D6em/B+4Y3La+k+Dg2fGF9ZCVNB8IVGu8XaWtBDZlms8H Q==; X-CSE-ConnectionGUID: zuKKChPgSsW2cFC39707Yg== X-CSE-MsgGUID: xpWjQSSJQpy4IW/zvpeH0Q== X-IronPort-AV: E=McAfee;i="6800,10657,11899"; a="93061794" X-IronPort-AV: E=Sophos;i="6.25,268,1779174000"; d="scan'208";a="93061794" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2026 23:39:15 -0700 X-CSE-ConnectionGUID: lISP/XTcQAKnLPuTYrK8Rg== X-CSE-MsgGUID: 9WKl1pnaQbymaQDOmUrbSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,268,1779174000"; d="scan'208";a="264702466" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2026 23:39:13 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, arun.r.murthy@intel.com, jani.nikula@linux.intel.com, suraj.kandpal@intel.com, Ankit Nautiyal Subject: [PATCH v5 08/12] drm/i915/dip: Add HAS_COMMON_SDP_TL macro Date: Tue, 8 Sep 2026 11:52:19 +0530 Message-ID: <20260908062224.2897987-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260908062224.2897987-1-ankit.k.nautiyal@intel.com> References: <20260908062224.2897987-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add a helper macro to detect CMN SDP TL support on platforms with display version 35 and above. v2: Use prefix drm/i915/dip. (Suraj) Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dip.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h index 600dabbf7372..e9959356226e 100644 --- a/drivers/gpu/drm/i915/display/intel_dip.h +++ b/drivers/gpu/drm/i915/display/intel_dip.h @@ -32,6 +32,16 @@ struct intel_crtc_state; #define HAS_EMP_AS_SDP_TL(__display) (DISPLAY_VERx100(__display) == 1401 || \ DISPLAY_VER(__display) >= 20) +/* + * CMN SDP TL: Common Secondary Data Packet Transmission Line. + * + * Xe3p_lpd introduces new register CMN_SDP_TL to program a common SDP + * Transmission line that will be used by the Hardware to position the + * SDPs. Along with this, another new register CMN_SDP_TL_STGR_CTL is + * also added to stagger the different SDPs. + */ +#define HAS_COMMON_SDP_TL(__display) (DISPLAY_VER(__display) >= 35) + u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state); void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state); -- 2.50.1